• 대한전자공학회논문지
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• 제26권10호
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• 대한전기학회논문지
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• 제33권2호
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• 한국전자파학회논문지
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• 제10권2호
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• pp.227-236
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• 1999

유한 차분 시간 영역법 (Finite Difference Time Domain Method FDTD)은 다양한 마이크로파 회로를 해석하는데 널리 이용된다. 그런데 이를 위한 기존의 소스 모델링 방법은 제한이 많고, 일반적인 형태의 회로 에 적용하기 어렵다. 따라서 본 논문에서는 여러 가지 마이크로파 회로를 효율적으로 해석하기 위해 내부 저 항 소스 모델링 (Internal Resistive Source M$\alpha$ieling)을 적용한다. 몇 개의 마이크로파 회로에 대하여 하드 소스 모델령 (Hard Source M$\alpha$ieling)을 이용한 결과와 비교하여 계산 시간이 현저하게 단축됨을 보이므로서 그 효율성을 입증하고, 기존의 소스 모텔링을 이용한 결과 및 측정치와도 비교함으로써 정확성을 입증한다.

• 한국초등과학교육학회지:초등과학교육
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• 제33권2호
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• pp.335-351
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• 2014

The 96 elementary school teachers' the degrees of understandings about the characteristics of the currents according to the connection methods of batteries in simple electric circuits were investigated. In this study, the concepts on the characteristics of currents according to the connection methods of batteries were divided 'the learned concepts' and 'the differentiated concepts'. The characteristics of the currents in the region of the larger resistance of load than the internal resistance of a battery were called the learned concepts, they are taught in the science curriculum. While the characteristics of the currents in the region of the smaller resistance of load than the internal resistance of a battery were called the differentiated concepts, they are not exposed clearly in the science curriculum. The results obtained in this study are as follows: The average score related to the learned concepts was relatively high, while the degree of the teachers' cognitions of the internal resistance of a battery and the resistance of wires were low. Also the average score related to the differentiated concepts was very low because it seems so new to the elementary school teachers. It strongly suggests that the elementary school teachers did not understand meaningfully the characteristics of the currents related to the connections of batteries on the ground of the cognitions of the internal resistances of batteries and the resistances of loads in simple electric circuits. Hence, they might experience difficulties due to the problems occurred in relation to the connections of batteries in the elementary school science lessons.

• 전자공학회논문지A
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• 제29A권11호
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1551-1555
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• 1987

This paper proposes a new test generation algorithm to detect stuck-open faults regardless of tine-skews in CMOS circuits. For testing for stuck-open faults regardless of time-skews, in this method, Hamming distance between the initialization pattern and the test pattern is made 1 by considering the responses of the internal gates. Therefore, procedure of the algorithm is simpler than that of the conventional methods because the line justification is unnecessary. Also, this method needs no extra hardware for testability and can be applied to random CMOS circuits in addition to two-level NAND - NAND CMOS circuits.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2007년도 춘계학술대회 논문집
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• pp.51-53
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• 2007

Ballasts for HID lamp need a igniter to start the lamp with very high voltage over several kV. Electronic ballasts use various internal igniter in electronic circuits. The paper describe the simulation method for designing the igniter, which helps selecting the component properly by estimating operation voltage and current in circuits.

• 대한전자공학회논문지
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• 제11권4호
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• pp.17-22
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• 1974

본논문에서는 조합논리회로의 결함검출에 관한 문제를 취급하였는데 먼저 fan-out가 없는 회로에 대한 결함검출방법을 논하고 이 방법을 fan-out가 있는 회로에 확장하였다. Fan-out가 있는 회로에서는 내부 fan-out점을 전후하여 fan-out가 없는 부분회로로 분리구분하고 우선 각 부분회로에 대한 최소테스트집합을 구한다. 다음에 각 부분테스트집합사이에서 최대한으로 병립가능한 테스트를 조합하여 전체회로에 대한 종합적인 입력테스트벡터를 구한다. 이와같은 절차에 의하면 테스트수가 최소인 완전테스트집합이 용이하게 구해질 뿐만 아니라 검출가능한 결함 및 불가능한 결함이 명확하게 판가름 된다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.31-32
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• 2006

A signal conditioning circuit for capacitive sensors was developed using a commercial single chip solution. Since capacitive displacement sensors can achieve high resolution and linearity, they have been widely used as precision sensors within the range of several hundred micrometers. However, they inherently have a limitation in low frequency range and some nonlinearity characteristics and so a specially designed signal conditioning circuit is needed to handle these properties. Up to now, several companies already have succeeded in the development of the capacitive sensors system and they are commercially available in the market. In this research, to construct the signal processing circuits more easily and simply, we used a universal LVDT signal conditioner (AD698). Since the AD698 provides one chip solution for a basic signal processing including modulation and demodulation using various internal components, we can build the processing circuits successfully with minimal additional circuits: a compensation circuits for the drift caused by the bias current of OP amplifiers and a fine adjustment circuit for the elimination of nonlinearity. The signal processing circuits shows nonlinearity less than 0.05% in the comparison with a laser interferometer.

• 전기학회논문지
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• 제57권10호
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• pp.1888-1892
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• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.