• Journal of the Korea Society for Simulation
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• v.17 no.1
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• pp.17-22
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• 2008

Double-binary turbo code has been adopted as an error control code of various future communication systems including wireless metropolitan area networks(WMAN) due to its powerful error correction capability. One of the components affecting the performance of turbo code is internal interleaver. In 802.16 d/e system, an almost regular permutation(ARP) interleaver has been included as a part of specification, however it seems that the interleaver is not optimized in terms of decoding performance. In this paper, we propose three optimization methods for the interleaver based on spatial distance, spread and minimum distance between original and interleaved sequence. We find optimized interleaving parameters for each optimization method and evaluate the performances of the proposed methods by computer simulation under additive white Gaussian noise(AWGN) channel. Optimized parameters can provide up to 1.0 dB power gain over the conventional method and furthermore the obtainable gain does not require any additional hardware complexity.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.250-257
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• 2011

This paper analyzes characteristic of the three-phase coupled inductor connected to ac source to effectively mitigate the high-frequency circulating current generated in parallel three-phase boost converters. The three-phase coupled inductor analysis presented in this paper uses the three-phase coupled inductor structure and voltage equations. Based on this analysis, the three-phase coupled inductor is added to the conventional low-frequency averaged model. As a result, the novel averaged model which can reduce the low and high-frequency circulating current simultaneously is developed. Using the zero-sequence component of the novel averaged model, each total inductance to the circulating current of the three-phase coupled inductor and line inductor can be obtained. Simulation and experiment results verify the usefulness of three-phase coupled inductor in parallel three-phase boost converters.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.26-32
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• 2022

This paper proposes a power system that includes a 120k W fuel cell DC-DC converter (FDC) and 30 kW bidirectional DC-DC converter (BHDC) for a 150 kW fuel-cell vehicle. With a high DC link voltage of 800 V, the efficiency and power density of the power electronic components are improved. Through the modular design of FDC and BHDC, electric components are shared, resulting in reduced mass production costs. The switching frequency of 30 kHz of full SiC devices and optimal design of coupled inductor reduce the volume, achieving a power density of 8.3 kW/L. Furthermore, a synergetic operation strategy using variable limiter control of FDC and BHDC was proposed to efficiently operate the fuel cell vehicle considering the fuel cell stack efficiency according to the load. Finally, the performance of the prototype was verified by Highway Fuel Economy Driving Schedule testing, EMI test, and the linked operation between FDC and BHDC. The full load efficiencies of the FDC and BHDC prototypes are 98.47% and 98.74%, respectively.

• Journal of Advanced Navigation Technology
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• v.27 no.5
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• pp.580-586
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• 2023

AESA radar is able to instantaneously and adaptively position and control the beam, and this enables to greatly improve multi-target tracking capability with high accuracy in comparison to traditional mechanically-scanned radar system. This paper is primarily concerned with the development of an efficient methodology for multi-target managenent with the context of multi-target environment employing AESA radar. In this paper, targets are stratified into two principal categories: currently displayed targets and non-display targets, predicated upon their relative priority. Displayed targets are subsequently stratified into TOI (target of interest), HPT (high priority target), and SAT (situational awareness target), based on the requisite levels of tracking accuracy. It also suggests rules for determining target priority management, especially in air-to-air mode including interleaved mode. This proposed approach was tested and validated in a SIL (system integration lab) environment, applying it to AESA radars mounted on aircraft.

• Progress in Medical Physics
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• v.18 no.1
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• pp.35-41
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• 2007

In this work practical considerations of a pulsed arterial spin labeling MRI are presented to reliable multi-slice perfusion measurements In the human brain. Three parameters were considered in this study. First, In order to improve slice profile and Inversion efficiency of a labeling pulse a high power Inversion pulse of adiabatic hyperbolic secant was designed. A $900^{\circ}$ rotation of the flip angle was provided to make a good slice profile and excellent Inversion efficiency. Second, to minimize contributions of a residual magnetization be4ween Interleaved scans of control and labeling we tested three different conditions which were applied 1) only saturation pulses, 2) only spotter gradients, and 3) combinations of saturation pulses and spotter gradients Applications of bo4h saturation pulses and spoiler gradients minimized the residual magnetization. Finally, to find a minimum gap between a tagged plane and an imaging plane we tested signal changes of the subtracted image between control and labeled Images with varying the gap. The optimum gap was about 20mm. In conclusion, In order to obtain high quality of perfusion Images In human brain It Is Important to use optimum parameters. Before routinely using In clinical studios, we recommend to make optimizations of sequence parameters.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3159-3174
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• 1997

This paper reports a research to develop a methodology and a tool for understanding of very large and complex real-time software. The methodology and the tool mostly developed by the author are called the Architecture-based Real-time Software Understanding (ARSU) and the Software Re/reverse-engineering Environment (SRE) respectively. Due to size and complexity, it is commonly very hard to understand the software during reengineering process. However the research facilitates scalable re/reverse-engineering of such real-time software based on the architecture of the software in three-dimensional perspectives: structural, functional, and behavioral views. Firstly, the structural view reveals the overall architecture, specification (outline), and the algorithm (detail) views of the software, based on hierarchically organized parent-chi1d relationship. The basic building block of the architecture is a software Unit (SWU), generated by user-defined criteria. The architecture facilitates navigation of the software in top-down or bottom-up way. It captures the specification and algorithm views at different levels of abstraction. It also shows the functional and the behavioral information at these levels. Secondly, the functional view includes graphs of data/control flow, input/output, definition/use, variable/reference, etc. Each feature of the view contains different kind of functionality of the software. Thirdly, the behavioral view includes state diagrams, interleaved event lists, etc. This view shows the dynamic properties or the software at runtime. Beside these views, there are a number of other documents: capabilities, interfaces, comments, code, etc. One of the most powerful characteristics of this approach is the capability of abstracting and exploding these dimensional information in the architecture through navigation. These capabilities establish the foundation for scalable and modular understanding of the software. This approach allows engineers to extract reusable components from the software during reengineering process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.