• Title/Summary/Keyword: Interfacial breakdown

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Effect of Space Charge Density and High Voltage Breakdown of Surface Modified Alumina Reinforced Epoxy Composites

  • Chakraborty, Himel;Sinha, Arijit;Chabri, Sumit;Bhowmik, Nandagopal
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.3
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    • pp.121-124
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    • 2013
  • The incorporation of 90 nm alumina particles into an epoxy matrix to form a composite microstructure is described in present study. It is shown that the use of ultrafine particles results in a substantial change in the behavior of the composite, which can be traced to the mitigation of internal charges when a comparison is made with conventional $Al_2O_3$ fillers. A variety of diagnostic techniques have been used to augment pulsed electro-acoustic space charge measurement to provide a basis for understanding the underlying physics of the phenomenon. It would appear that, when the size of the inclusions becomes small enough, they act cooperatively with the host structure and cease to exhibit interfacial properties. It is postulated that the $Al_2O_3$ particles are surrounded by high charge concentrations. Since $Al_2O_3$ particles have very high specific areas, these regions allow limited charge percolation through $Al_2O_3$ filled dielectrics. The practical consequences of this have also been explored in terms of the electric strength exhibited. It would appear that there was a window in which real advantages accumulated from the nano-formulated material. An optimum filler loading of about 0.5 wt.% was indicated.

The Study on the Dry Floor Tile Unit System used Resin Mat (수지매트를 이용한 바닥타일 건식공법 시스템에 관한 연구)

  • 김성식;임남기;정병훈;정재영;정상진
    • Journal of the Korea Institute of Building Construction
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    • v.1 no.2
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    • pp.185-190
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    • 2001
  • The purpose of this study is the development of practical Dry floor tile unit method that settle the defect of a wet method and designed for resin mat. With use of PE resin which is confirmed the basic property, it is developed that resin mat, joint-sealing compound with fixed form and space management to Dry floor tile unit method. The result of this study is below. 1) To acquire above the 4kgf/$\textrm{cm}^2$ - construction specification criterion, the bonding space that between resin mat and tile has to occupy the 50% of resin mat module space(10,000$\textrm{cm}^2$). 2) Criteria of bonding part plane is below. simpleness of metal form. productivity, uniform quality after injection molding cooling, easy cutting for remain space management, adhesive property, construction ability, transformation of a severed piece under pressure and so on. 3) To get the shape that could protect the interfacial breakdown, it is designed that resin mat and tile are unified after the bond input. 4) Adapted joint-sealing compound is the material of urethane kinds wedge form. Resin mat has the water passageway that could drain the water. 5) To manage the severed piece of tile, the resin mat is likely to divide the half and the quarter and the plastic drainage is developed in the severed piece.

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Cavity and Interface effect of PI-Film on Charge Accumulation and PD Activity under Bipolar Pulse Voltage

  • Akram, Shakeel;Wu, Guangning;Gao, GuoQiang;Liu, Yang
    • Journal of Electrical Engineering and Technology
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    • v.10 no.5
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    • pp.2089-2098
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    • 2015
  • With the continuous development in insulation of electrical equipment design, the reliability of the system has been enhanced. However, in the manufacturing process and during operation under continues stresses introduce local defects, such as voids between interfaces that can responsible to occurrence of partial discharge (PD), electric field distortion and accumulation of charges. These defects may lead to localize corrosion and material degradation of insulation system, and a serious threat to the equipment. A model of three layers of PI film with air gap is presented to understand the influence of interface and voids on exploitation conditions such as strong electrical field, PD activity and charge movement. The analytical analysis, and experimental results are good agreement and show that the lose contact between interfaces accumulate more residual charges and in consequences increase the electric field intensity and accelerates internal discharges. These residual charges are trapped charges, injected by the electrodes has often same polarity, so the electric field in cavities increases significantly and thus partial discharge inception voltage (PDIV) decreases. Contrary, number of PD discharge quantity increases due to interface. Interfacial polarization effect has opposite impact on electric field and PDIV as compare to void.

$Y_{2}O_3$ Films as a Buffer layer for a Single Transistor Type FRAM (단일 트랜지스터용 강유전체 메모리의 Buffer layer용 $Y_{2}O_3$의 연구)

  • Jang, Bum-Sik;Lim, Dong-Gun;Choi, Suk-Won;Mun, Sang-Il;Yi, Jun-Shin
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1646-1648
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    • 2000
  • This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.

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Reactive RF Magnetron Sputter Deposited $Y_2O_3$ Films as a Buffer Layer for a MFIS Transistor

  • Lim, Dong-Gun;Jang, Bum-Sik;Moon, Sang-Il;Junsin Yi
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.47-50
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    • 2000
  • This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

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Electrical and thermal properties of polyamideimide-colloid silica nanohybrid for magnetic enameled wire

  • Han, S.W.;Kang, D.P.
    • Journal of Ceramic Processing Research
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    • v.13 no.spc2
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    • pp.428-432
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    • 2012
  • Polyamidimide (PAI)-colloidal silica (CS) nanohybrid films were synthesized by an advanced sol-gel process. The synthesized PAI-CS hybrid films have a uniform and stable chemical bonding and there is no interfacial defects observed by TEM. The thermal degradation ratio of PAI-CS (10 wt%) hybrid films is delayed by 100 ℃ compared with pure PAI sample determined by on set temperature range in TGA. The dielectric constant of PAI-CS (10 wt%) hybrid films decreases with increasing CS content up to about 5 wt% but increases at higher CS content, which is not explained simply by effective medium therories (EMT). The duration time of PAI-CS (10 wt%) hybrid coil is 38 sec, which is very longer than that of pure PAI coil sample. The PAI-CS (10 wt%) hybrid film has a higher breakdown voltage resistance than the pure PAI film at surge environment and exhibits superior heat resistance. The PAI-CS (10 wt%) sample shows the advanced and stable thermal emission properties in transformer module compared with the pure PAI sample. This result illustrates that the advanced thermal conductivity and expansion properties of PAI-CS sample in the case of appropriate sol-gel processes brings the stable thermal emission in transformer system. Therefore, new PAI-CS hybrid samples with such stable thermal emission properties are expected to be used as a high functional coating application in ET, IT and electric power products.

The Effects of Electrode Materials on the Electrical Properties of $Ta_2O_5$ Thin Film for DRAM Capacitor (DRAM 커패시터용 $Ta_2O_5$ 박막의 전기적 특성에 미치는 전극의존성)

  • Kim, Yeong-Wook;Gwon, Gi-Won;Ha, Jeong-Min;Kang, Chang-Seog;Seon, Yong-Bin;Kim, Yeong-Nam
    • Korean Journal of Materials Research
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    • v.1 no.4
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    • pp.229-235
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    • 1991
  • A new electrode material for $Ta_2O_5$ capacitor was developed to obtain both high dielectric constant and improved electrical properties for use in DRAM. High leakage current and low breakdown field of as-deposited $Ta_2O_5$ film on Si is due to the reduction of $Ta_2O_5$ by silicon at $Ta_2O_5$/electrode interface. $Dry-O_2$ anneal improves the electrical properties of $Ta_2O_5$ capacitor with Si electrode, but it thickens the interfacial oxide and lowers the dielectric constant, subsequently. $Ta_2O_5$ capacitor with TiN exectrode shows better electrical properties and higher dielectric constant than post heat treated $Ta_2O_5$ film on Si. No interfacial oxide layer at $Ta_2O_5$/TiN interface suggests that there\`s no Interaction between $Ta_2O_5$ and electrode. TiN is a adequate electrode material for $Ta_2O_5$ capacitor.

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A Study on the Dielectric Characteristics and Microstructure of $Si_3N_4$ Metal-Insulator-Metal Capacitors ($Si_3N_4$를 이용한 금속-유전체-금속 구조 커패시터의 유전 특성 및 미세구조 연구)

  • 서동우;이승윤;강진영
    • Journal of the Korean Vacuum Society
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    • v.9 no.2
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    • pp.162-166
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    • 2000
  • High quality $Si_3N_4$ metal-insulator-metal (MIM) capacitors were realized by plasma enhanced chemical vapor deposition (PECVD). Titanium nitride (TiN) adapted as a diffusion barrier reduced the interfacial reaction between $Si_3N_4$ dielectric layer and aluminum metal electrode showing neither hillock nor observable precipitate along the interface. The capacitance and the current-voltage characteristics of the MIM capacitors showed that the minimum thickness of $Si_3N_4$ layer should be limited to 500 $\AA$ under the present process, below which most of the capacitors were electrically shorted resulting in the devastation of on-wafer yield. According to the transmission electron microscopy (TEM) on the cross-sectional microstructure of the capacitors, the dielectric breakdown was caused by slit-like voids formed at the interface between TiN and $Si_3N_4$ layers when the thickness of $Si_3N_4$ layer was less than 500 $\AA$. Based on the calculation of thermally-induced residual stress, the formation of voids was understood from the mechanistic point of view.

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A Study on the Engine Oil Resistant Behaviors of Room Temperature Vulcanizing Silicone Adhesives (상온 경화형 실리콘 접착제의 내엔진 오일성에 관한 연구)

  • Park, Soo-Jin;Jin, Fan-Long;Kim, Jong-Hak;Joo, Hyeok-Jong;Kim, Joon-Hyung
    • Elastomers and Composites
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    • v.40 no.3
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    • pp.196-203
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    • 2005
  • In this work, the engine oil resistant evaluation and breakdown analysis of room temperature vulcanizing silicone adhesives were performed through the surface properties, thermal stabilities, adhesive strength, and morphology measurements. As a result, the permeation of engine oil into adhesive specimens was carried out from surface to center in the specimens. And the oil content in the adhesive specimens was increased and the Si-O-Si bond of the adhesives was decomposed with increasing the aging time. The TGA results indicated that the thermal degradation was mainly occurred at under and surfaces of the specimens. The tensile strength, elongation, and adhesive strength of the adhesives were significantly decreased after the engine oil resistant tests, which could be attributed to the initial lose of adhesive properties resulting from the engine oil absorption and thermal aging. And the failure mode of the adhesive specimens was changed from cohesive failure to interfacial failure.

The Electrical Properties of Post-Annealing in Neutron-Irradiated 4H-SiC MOSFETs (중성자 조사한 4H-SiC MOSFET의 열처리에 의한 전기적 특성 변화)

  • Lee, Taeseop;An, Jae-In;Kim, So-Mang;Park, Sung-Joon;Cho, Seulki;Choo, Kee-Nam;Cho, Man-Soon;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.4
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    • pp.198-202
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    • 2018
  • In this work, we have investigated the effect of a 30-min thermal anneal at $550^{\circ}C$ on the electrical characteristics of neutron-irradiated 4H-SiC MOSFETs. Thermal annealing can recover the on/off characteristics of neutron-irradiated 4H-SiC MOSFETs. After thermal annealing, the interface-trap density decreased and the effective mobility increased in terms of the on-characteristics. This finding could be due to the improvement of the interfacial state from thermal annealing and the reduction in Coulomb scattering due to the reduction in interface traps. Additionally, in terms of the off-characteristics, the thermal annealing resulted in the recovery of the breakdown voltage and leakage current. After the thermal annealing, the number of positive trapped charges at the MOSFET interface was decreased.