• Transactions of the Korean Society of Machine Tool Engineers
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• v.12 no.6
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• pp.104-111
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• 2003

In order to collect the engine performance data and determine optimum engine conditions, engine performance test based on interface unit were tested This paper was carried out that engine' performance was developed using interface unit between personal computer and diesel engine. The results of the study are summarized as follows: Interface unit was developed. By using PAL, simulation was carried in order to logic's inspection. From this tea NO$_{x}$ were decreased, otherwise PM were increased. By using EGR system PM were increased by twice in the high load ranges, it was not seen to come into effect in the low load ranges. This system was tested D-l3 mode, the results were decreased more than 50% in the NO$_{x}$ emission.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.195-197
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• 2006

In this paper, an interface unit is designed to efficiently monitor transmission data in Controller Area Network(CAN)-based control systems. The CAN uses a serial multi master communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1Mbps. The interface unit is composed of a DSP controller which collects data on the CAN bus and transfers data to a personal computer via serial communication to save and display of interesting signals. The experimental system consists of three DSP controllers which represent electronic control units of a vehicle, an interface unit for analysing the data on the bus, and a graphic monitoring program coded on the Windows platform. The validity and the effectiveness of the proposed simple type of CAN interface unit are shown through the experimental results.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.5
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• pp.88-92
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• 2006

Proto Flight Model of Reaction Wheel Assembly Interface Unit(RIU) for STSAT-2 was developed. The RIU of STSAT2 has three major functions for interface between satellite system and RWAs. It has switches for RWA main power, communication Mux. and communication line driver.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.51-57
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• 1999

This thesis is written about the Wired Logic Type Unit in developing equipment that the load is driven, that the interface unit connect with 1 Scan time to PO30 of operated PLC output contact with that a sensing signal of Temperature Sensor RSD Pt $100\Omega$ let generate the relay output of temperature controller and input the PLC. The PLC Test Kit in country that the PLC to be programmed at the PLC education place is able to drive the load, is done to do a education of PLC on status that interface process between PLC and load are disregarded. As Developing Kit for supplement this point, when the relay output of temperature controller to use Pt 100 of temperature sensor as mentioned on the former among every kinds of sensor feed back to the input of the PLC, as the equipment to act with real time system that the output contact of PLC operated to insert the WLTIJ among PC, PLC and the load, it can understand and see very easy the main principle of PLC use. The structure of WLTU to be a interface unit of load separated as to the point of contact and noncontact, sensor, indicating lamp and A contact and B contact that is belong to driving part, and a motor is belong to loading part.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.404-410
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• 1991

In this paper,a network interface unit of token-passing bus network and its driving software are implemented based on Mini-MAP. This network interface unit performs the function of MAC layer which is responsible for transmission and reception of frames as well as the management of logical ring. The driving software performs the management of data buffer and the report of errors, if ocoured, to the higher layer. Motorola MC68824 of is used as a TBC(Token Bus Controller) and Intel80186 as a CPU for network interface unit. The operation of network interface unit is verified by self-test which checks the functioning of TBC and CPU. In addition each module of driving software is tested to check the functions regarding transmission and reception of frames.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.6
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• pp.520-526
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• 2013

This study presents the unit control of a PC (Personal Computer) program using multiple smartphones based on ad hoc communication. A design of the data packet that multiple smartphones send to a computer, and a framework that manages and controls the unit in a computer after analyzing the data packet, are proposed. As a result, multiple users are able to control their own units using their smartphones while seeing the monitor connected to a computer. In other words, multiple users can share the same game in a computer or control their units embedded in a system using their smartphones. An experimental result shows that a racing game in a PC can be realized by the proposed communication interface, where four iPhones are used to control their units in a computer. Thus, the proposed framework can be effectively used for unit control in a PC using multiple smartphones.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.1-7
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• 1996

In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1999.04a
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• pp.77-77
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• 1999

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.