• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.5
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• pp.343-354
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• 2009

In this paper, a magnetic-less dc-dc switching converter realizing an integrable power conversion system is described. Instead of magnetic devices, the inductive impedance range of piezoelectric transducers is utilized to store and resonate the energy for soft-switching. Piezoelectric devices have no windings and deliver the power by the electrodes, which lead to mass product through semiconductor-manufacturing process. This paper presents a resonant-type step-up dc-dc power converter employing a disk-type piezoelectric transducer, analyzing the operation principles and the frequency control characteristics. Also, a topology extension of the single stage converter into cascaded multi-stage is presented and analyzed with the operation principles and control characteristics. For verification of the analysis, a 10W output dc-dc power converter hardware was implemented. The hardware experiments shows a good frequency control and power efficiency greater than 96% in the single stage. A hardware prototype of the extended multi-stage one was also realized and tested. The results shows that the converter has the same frequency control performance and high efficiency such as 93%.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1121-1124
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• 2002

In this paper, an IC realization of a cell-network type SC DC-DC converter is reported. To achieve small and low-cost realization, the converter is designed by using a 1.2 $\mu\textrm{m}$ CMOS technology. The CMOS implemented converter will be useful as a building block of various mobile equipments since step-up and step-down voltages can be provided at one time. Concerning the proposed DC-DC converter, SPICE simulatiorls are performed to investigate the characteristics of the circuit. The SPICE simulations show that, the efficiency of the simulated circuit is more than 95 %. From the layout design using a CAD tool, MAGIC, the VLSI chip is fabricated in the chip fabrication program of VLSI Design and Education Center(VDEC), the University of Tokyo with the collaboration by On-Semiconductor. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.