• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• The KIPS Transactions:PartD
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• v.9D no.2
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• pp.289-296
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• 2002

The web, which is most actively used in the internet environment, is changing educational system. Students usually prefer the interactive and multimedia learning aids based on web applications and web media to static web pages. The former is known to enhance the effectiveness of learning. This paper proposes a study system which involves effective adaptation to the various changing factors of learners' progress and the corresponding automated evaluation system. Conventional evaluation utilizes normalized method, where the learning objectives generally set by the instructors or educational operators/administrators are usually pursued rather than the interest of the individual learners, which is not ideal for the computer-based learning. Web-based project-oriented learning system provokes the mutual participations among the users, operators, and administrators in understanding the jobs to be performed and the effort to enhance the progressive developments of knowledge and application capabilities. In this Paper, an automated evaluation system is implemented, where the instructors and web-operators/administrators work as hosts for education. The learners take advantage of user-oriented comparative learning and pattern design. The design and implementation of the project-oriented evaluation methods performed in the internet/intranet environments are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• International Journal of Advanced Culture Technology
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• v.1 no.2
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• pp.24-32
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• 2013

This paper determined students' ranks of difficulty on the use of materials in terms of 1) understanding the layout of the learning materials, 2) reading comprehension of the learning materials, and 3) realization on relevance to needs of the learning materials. It also determined students' 4) rank and frequency of attitude on the materials. With the data gathered through 128 survey questionnaires, 7 focused group discussions, and 10 interviews, the results were found out that there was an inappropriate assessment procedure set by this particular university. The researcher concludes that: 1) design of four types of classes by just using the two textbooks with their respective workbooks is grammar-based with limited conversation activities; 2) placement for these students in one big class size was implemented without considering their common interest and motivation and language levels; and, 3) qualification of teachers teaching these EFL students did not support students' real needs and the language program itself. Content professors who were made to teach may have the ability to input learning, but their teaching styles may differ from the ones who are real English teachers. This paper then recommends that teachers and school administration should have an appropriate placement exam before students attend the class, especially in a big class size. There could only be a few problems among students in one big class size when students' level of competence is proportioned. With this, topics and conversation activities can even be more flexible with the maneuver of art of questioning, various dimensions of thinking, strategic competence, learning attitude or behavior, etc. to ensure sustenance of communicative mode and level of interest and motivation in the classroom. Grammar-based instruction can only be taught when a need arises. Thus, the course description of each class will be able to transact the objectives ready for developing students' communication competence. Moreover, proper measurement can be utilized to validly assess the amount of students' learning and the progress of language curriculum design in terms of materials selection and teaching approach.

• Journal of the Korean Institute of Landscape Architecture
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• v.44 no.1
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• pp.51-65
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• 2016

A syllabus can be considered to be a masterplan for good educational results. This study tries to diagnose the current status of landscape architectural design education and suggest improvement strategies for better landscape design courses through the analysis of the syllabi of mid-level landscape design studio classes collected from the four-year undergraduate programs. The findings and suggestions are as follows. First, it is necessary to take advantage of a syllabus as a contract as well as a plan and a learning tool. Second, it is crucial to make more detailed statement from the perspectives of learners. Third, more customized components for design courses should be developed; the syllabus should give the structure of a design class as an integration and synthesis of other courses. Fourth, it is necessary to increase the interrelationship and relevance among the components, especially between course objectives and evaluation criteria, and course activities and references. Fifth, a syllabus needs to function as a communication tool in a flexible manner. Sixth, a syllabus needs to give a comprehensive information about the site and the design project. Finally, instructors need to introduce a set of detailed evaluation rubrics or criteria acceptable to students in order to increase the fairness and transparency of the evaluation.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.