• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.5
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• pp.251-257
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• 2014

Digital RDA system is retransmit into the opposite direction of the incident signals. Digital RDA system have a disadventage that this system do not signal classification in multipath environment. because multipath signal is shown as vector sum of multipath signal, digital RDA system required complex signal process for multipath signal classification. In this paper, to solve these problem we propose hybrid digital RDA system which combination of the MUSIC algorithm and the digital RDA system. Proposed system has two modes. First mode is digital RDA mode. Secornd mode is digital beamforming mode. Digital RDA mode is used in situations where the less the impact of multipath. Digital beamforming mode is applied to multipath effects is greater. In secornd mode, we find optimal path using MUSIC algorithm. After than the proposed system uses only the optimal path. Through the proposed system in a multipath environment with digital RDA can be used to supplement a disadvantage.

• Journal of IKEEE
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• v.24 no.4
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• pp.1122-1128
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• 2020

Bandwidth Extension refers to restoring and expanding a narrow band signal(NB) that is damaged or damaged in the encoding and decoding process due to the lack of channel capacity or the characteristics of the codec installed in the mobile communication device. It means converting to a wideband signal(WB). Bandwidth extension research mainly focuses on voice signals and converts high bands into frequency domains, such as SBR (Spectral Band Replication) and IGF (Intelligent Gap Filling), and restores disappeared or damaged high bands based on complex feature extraction processes. In this paper, we propose a model that outputs an bandwidth extended signal based on an autoencoder among deep learning models, using the residual connection of one-dimensional convolutional neural networks (CNN), the bandwidth is extended by inputting a time domain signal of a certain length without complicated pre-processing. In addition, it was confirmed that the damaged high band can be restored even by training on a dataset containing various types of sound sources including music that is not limited to the speech.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.159-162
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• 2005

Recently, due to rapid developments of wireless communication and digital TV, modern society needs to process of aquisition, storage and transmission of much information. So the importance of signal processing is increasing and various digital filters are used in the two-dimensional signal such as image. And kinds of these digital filters are IIR(infinite impulse response) filter and FIR(finite impulse response) filter. And FIR filter which has the phase linearity, the easiness of creation and stability is applied to many fields. In design of this FIR filter, flatness property is a important factor in pass-band and stop-band. In this paper, we designed a 2-D Circular FIR filter using the Bernstein polynomial, it is presented flatness property in pass-band and stop-band. And we simulated the designed filter with noisy test image and compared the results with existing methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.41-45
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• 1985

A degradation of the signal-to-noise ratio (SNR) in a digital moving target indicator system (DMTI System) can be Improved by weighting of the DMTI output pulses before the integration process. and it Is shown that the signal-to-noise ratio Is unproved as the nunlber of delay line cancellers. It is Known that signal-to-noise ratio obtained with optimum weighting is greater than that obtained with binomial weighting. An improvement performance of the signal-to-noise ratio for each case is presented through the results or a computter simulation.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.68-74
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• 2011

In this paper, we present the enhancement results such as availability and accuracy using the GPS L1 and Galileo E1 signal combination. To enhance the acquisition and tracking performance of signal processing in GNSS receiver. several tracking loops with integrator, discriminator, and loop filter module are applied. Also, this paper presents the performance comparison results between prototype receiver equipped with hardware board and software receiver. Also the tracking loop performance of real hardware receiver is verified by comparing with tracking accuracy, sensitivity occurred by the Spirent simulator. Especially, to process the Galileo E1 signal, it is used the a power early late type which is the typical type for DLL discriminator.

• The Journal of the Acoustical Society of Korea
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• v.10 no.4
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• pp.5-11
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• 1991

This paper suggests a segmentation method of speech signal into phonemic units. The suggested segmentation system is speaker-independent and performed without anyprior information of speech signal. In segmentation process, we first divide input speech signal into purevoiced region and not pure voiced speech regions. After then we apply the second algorithm which segments each region into the detailed phonemic units by using the voiced detection parameters, i.e., the time variation of 0th LPC cepstrum coefficient parameter and the ZCR parameter. Types of speech, used to prove the availability of segmentation algorithm suggested in this paper, are the vocabulary composed of isolated words and continuous words. According to the experiments, the successful segmentation rate for 507 phonemic units involved in the total vocabulary is 91.7%.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.8
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• pp.11-19
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• 1994

The matching probability P(ο/$\lambda$), of the signal sequence(ο) observed for a finite time interval with a HMM (Hidden Markov Model $\lambda$) indicates the probability that signal comes from the given model. By utilizing the fact that the probability represents matching score of the observed signal with the model we can recognize an unknown signal pattern by comparing the magnitudes of the matching probabilities with respect to the known models. Because the algorithm however uses floating point variables during the computing process hardware implementation of the algorithm requires floating point units. This paper proposes an integer algorithm which uses positive integer numbers rather than float point ones to compute the matching probability so that we can economically realize the algorithm into hardware. The algorithm makes the model parameters integer numbers by multiplying positive constants and prevents from divergence of data through the normalization of variables at each step. The final equation of matching probability is composed of constant terms and a variable term which contains logarithm operations. A scheme to make the log conversion table smaller is also presented. To analyze the qualitive characteristics of the proposed algorithm we attatch simulation result performed on two groups of 10 hypothetic models respectively and inspect the statistical properties with repect to the model order the magnitude of scaling constants and the effect of the observation length.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.9-16
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• 1997

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.