• Journal of Information Processing Systems
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• v.6 no.4
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• pp.537-552
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• 2010

Software Debugging is the most time consuming and costly process in the software development process. Many techniques have been proposed to isolate different faults in a program thereby creating separate sets of failing program statements. Debugging in parallel is a technique which proposes distribution of a single faulty program segment into many fault focused program slices to be debugged simultaneously by multiple debuggers. In this paper we propose a new technique called Faulty Slice Distribution (FSD) to make parallel debugging more efficient by measuring the time and labor associated with a slice. Using this measure we then distribute these faulty slices evenly among debuggers. For this we propose an algorithm that estimates an optimized group of faulty slices using as a parameter the priority assigned to each slice as computed by value of their complexity. This helps in the efficient merging of two or more slices for distribution among debuggers so that debugging can be performed in parallel. To validate the effectiveness of this proposed technique we explain the process using example.

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1382-1396
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• 2017

In this paper, we analyze a recently proposed semi-fragile watermarking scheme based on local binary pattern (LBP) operators, and note that it has a fundamental flaw in the design. In this work, a binary watermark is embedded into image blocks by modifying the neighborhood pixels according to the LBP pattern. However, different image blocks might have the same LBP pattern, which can lead to false detection in watermark extraction process. In other words, one can modify the host image intentionally without affecting its watermark message. In addition, there is no encryption process before watermark embedding, which brings another potential security problem. To illustrate its weakness, two special copy-paste attacks are proposed in this paper, and several experiments are conducted to prove the effectiveness of these attacks. To solve these problems, an improved semi-fragile watermarking based on LBP operators is presented. In watermark embedding process, the central pixel value of each block is taken into account and Arnold transform is adopted to guarantee the security of watermark. Experimental results show that the improved watermarking scheme can overcome the above defects and locate the tampered region effectively.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1868-1879
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• 1996

There are limitations to process high bandwidth traffic in B-ISDN with mesh- topology single bus architecture of current mobile communication system. And, it is impossible to import ATM switch using fixed length packet rather than variable length packet. Some implementations are able to process variable length packet, but there are some problems such as pre-processing for synchronization and bit delay. In this paper, we design a concentrator that can manipulate variable length packet without additional pre-process. There is on bit delay for packet starting signal in input interface, So it is more efficient to process packets, such that the concentrator can reduce he processing time as $\ulcornerlog2N\lrcorne＋1$ bit-time rather than N bit-time delay in ordinary concentrator. It is expected that the mobile communication system with partial mesh topology bus adopting the knockout switch architecture can process high bandwidth traffic in B-ISDN.

• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.163-169
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• 2006

So far, little research has been conducted into developing a QAPM (Quality Assurance Process Model) for telecommunications applications on the basis of TMN. This is the first trial of the design of TMN-based QAPM on fault management with UML. A key attribute of the QAPM is that it can easily identify current deficiencies in a legacy system on the basis of TMN architecture. Using an empirical comparison with the legacy systems of a common carrier validates the QAPM as the framework for a future mode of the operation process. The results indicate that this paper can be used to build ERP(Enterprise Resource Planning) for a telecommunications fault management solution that is one of the network management application building blocks. The future work of this paper will involve applying the QAPM to build ERP for RTE (Real Time Enterprise) fault management solution and more research on ERP design will be necessary to accomplish software reuse.

• The Transactions of the Korea Information Processing Society
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• v.7 no.5
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• pp.1409-1418
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• 2000

Auditing plays a very important role in the process of developing and managing good quality software. The software developing proces should be audited precisely especially in the test phase. Up to the present, because auditing has depended on the auditor's experience of developing and auditing software, it has been impossible to audit objectively. It is limited to audit systematically and objectively because auditing process isn't systematized. In this paper, the auditing model to solve several problems in present auditing is suggested, a test phase audit system is developed, and the system is applied to the actual auditing process. Consequently, software administrators can establish effective software management, software developers can be supported by a highly reliable and quality software development tool, and auditors can be offered an objective audit standard.

• The Korean Journal of Applied Statistics
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• v.21 no.6
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• pp.997-1006
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• 2008

This paper proposes a new model by combining an infinite-server queueing model for multi-task processing software system with a perfect debugging model based on Markov process with two types of faults suggested by Lee et al. (2001). We apply this model for module and integration testing in the testing process. Also, we compute several measure, such as the expected number of tasks whose processes can be completed and the task completion probability are investigated under the proposed model.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.191-194
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• 2005

SU-8 is a epoxy based photoresist designed for MEMS applications, where a thick, chemically and thermally stable image are desired. However SU-8 has proven to be very sensitive to variation in processing variables and hence difficult to use in the fabrication of useful structures. In this paper, negative SU-8 photoresist processed has been characterized in terms of delamination, based on a full factorial designed experiment. Employing the design of experiment (DOE), a process parameter is established, and analyzing of full factorial design is generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.

• Journal of the Korea Society for Simulation
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• v.6 no.2
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• pp.71-79
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• 1997

In this paper, operations system was designed for the centralization of data processing of various state information from the facilities of mobile communication network. And the system performance experimental system module was measured and analyzed from the designed experimental system module. The configuration of system design was presented with the centralized type to monite and control the facilities of mobile communication network in the central office. The communication process design of the internal system was implemented with the resource of message queue having a excellent transmission ability for processing of a great quantity of information in the inter-process communication among communication resources of UNIX system. The process with a server function from the internal communication processes was constructed with a single server or a double server according to the quantity of operations and implemented with the policy of the presented server. And then, we have measured performance elements in accordance with the change of input parameters from the designed experimental module : response time, waiting time, buffer length, the maximum quantity existing in message queue. And from these results, we have compared and analyzed the system state each server algorithm according to performance variations.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.409-412
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• 2004

The technique and process for the acquisition of components by searching and testing the reusable components using Web Service in the CASE tools for component-based application development are proposed. The technique and process for the notice of components using Web Service in order to reuse developed components are also proposed. As using the technique and process, a repository does not need to construct and the reusability of components will rise because components are easily and efficiently searched using Web Service. Furthermore, it is easy to develop application through the plug-and-play of components which are acquired using Web Service, and errors of application by reused components will be minimized because proper components are acquired after pretesting reusable components in the analysis and the architecture phase.