• Title/Summary/Keyword: Information Bottleneck Method (IBM)

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Classification of Rural Villages Using Information Theory (정보이론을 이용한 농촌마을 권역화 연구)

  • Lee, Ji-Min;Lee, Jeong-Jae
    • Journal of The Korean Society of Agricultural Engineers
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    • v.49 no.1
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    • pp.23-33
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    • 2007
  • Classification results of rural villages provide useful information about rural village characteristics to select similar villages in rural development project; many researches about regional classification have been practiced. Recently rural amenity was introduced as an alternative for rural development, and rural villages have been surveyed to find potential resources for rural development by 'Rural Amenity Resources Survey Project'. Accumulated information through this survey project could be used to classify rural villages. However existing rural classification method using statistical data is not efficient method to use rural amenity resources information described with text. We introduced Information Bottleneck Method (IBM) based on information theory and implemented this method to classification with rural amenity resources information of Yanggang-myen, Yeongdong-gun in Chungbuk province.

An On-chip Cache and Main Memory Compression System Optimized by Considering the Compression rate Distribution of Compressed Blocks (압축블록의 압축률 분포를 고려해 설계한 내장캐시 및 주 메모리 압축시스템)

  • Yim, Keun-Soo;Lee, Jang-Soo;Hong, In-Pyo;Kim, Ji-Hong;Kim, Shin-Dug;Lee, Yong-Surk;Koh, Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.125-134
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    • 2004
  • Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.