• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.789-795
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• 2011

It is necessary to accurately predict converter losses for optimized design of a high-power DC-DC converter. The losses of switching devices and inductor among the elements of the converter take significantly greater proportion. The current ripple will be determined by the size of the inductance and this inductance value varies depending on the DC amount of inductor current. As the inductance changes according to load current, the change influences not only the inductor loss itself but also the total converter loss. In this paper, for more accurate design of a bi-directional DC-DC converter for 30kW-class energy storage system, more accurate computational model is proposed considering inductance variation according to the load current change. The inductance changes using variable magnetic cores are verified and converter efficiency is tested through simulations and experiments.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.9
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• pp.537-544
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• 2002

This paper describes a comparative analysis of soft switching boost converters through design, production and experiment. Soft switching boost converters are designed to satisfy the condition of input voltage 170-265Vac, output voltage 400Vdc, output current 5A, output power 20W-2000W and unit power factor. In addition, parameter values are designed so that system operation can be compared under this is similar conditions. The efficiency of the combined inductor soft switching boost converter was 97.63% with 1011 load better than that of other boost converter types. The combined inductor soft switching converter has simple circuit construction and low switching loss. EMI resulted by the switching noise, and harmonic distortion.

• Journal of Power Electronics
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• v.14 no.4
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• pp.621-631
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• 2014

To invigorate the tapped-inductor boost (TIB) topology in emerging high step-up applications for off-grid products, a lossless snubber consisting of two capacitors and three diodes is proposed. Since the switch voltage stress is minimized in the proposed circuit, it is allowed to use a device with a lower cost, higher efficiency, and higher availability. Moreover, since the leakage inductance is fully utilized, no effort to minimize it is required. This allows for a highly productive and cost-effective design of the tapped-inductor. The proposed circuit also shows a high step-up ratio and provides relaxation of the switching loss and diode reverse-recovery. In this paper, the operation is analyzed in detail, the steady-state equation is derived, and the design considerations are discussed. Some experimental results are provided to confirm the validity of the proposed circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.311-320
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• 2008

In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Journal of Industrial Technology
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• v.29 no.B
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• pp.101-105
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• 2009

A 1.571GHz LC VCO with optimized spiral inductor for GPS receiver is designed in 130nm CMOS process. The phase noise of the VCO has been reduced the use of high Q inductor and on chip filter. It has phase noise of -91dBc/Hz, -111dBc/Hz, and -131dBc/Hz at 10kHz, 100kHz, and 1MHz offset frequencies from the carrier, respectively. This VCO consumes 2mA from a 0.6V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.35-44
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• 2001

A simulated floating inductor using two fully-differential OTA's and a capacitor is presented. The theory of operation is described and experimental results are used to verify theoretical predictions. The results show close agreement between predicted behavior and experimental performance. The proposed floating inductor has about two times higher Q factor than conventional designs. The application of the inductor to a ladder type third order ellitic low pass filer is also presented.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.3
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• pp.31-39
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• 2012

This paper presents a high efficiency coupled inductor boost DC-DC converter that uses a simple clamp circuit and the coupled inductor and thus overcomes output voltage limit of the conventional boost converter. The proposed converter solves problems of voltage stress of the power semiconductor switch and reverse recovery of the output diode using a simple clamp circuit composed of a diode and a capacitor, and thus the converter improves its total efficiency. In this paper, the operational principle of the proposed converter is explained by each mode and then a design example for the prototype converter based on the explanation is shown. And good performance of the proposed converter is verified through experimental results of the prototype converter that is implemented with the designed circuit parameters.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.785-787
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• 2005

This paper addresses the small-signal analysis of the multi-phase interleaved boost converter with the coupled inductors operated in the continuous inductor current mode. The generalized and analytical expressions for the transfer functions of interest are derived for various inductor couplings. The dynamic characteristics are analyzed according to the inductor couplings and verified experimentally. The proposed frequency models will be very useful to design the dynamic controllers of the multi-phase interleaved boost converters.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.290-296
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• 2014

This paper presents a design strategy for the control of the Z-source inverter (ZSI). For the Z-network capacitor voltage control, the average current model is derived to describe the dynamics of the voltage control and the controller outputs the average current command for the capacitor. Z-network inductor current reference is derived from the average current model of the Z-network capacitor. The inner current control loop outputs the average voltage command for the Z-network inductor and the shoot-through duty ratio of the ZSI is calculated from the output using the average voltage model of the Z-network inductor. The gain values of the current and voltage controllers are directly obtained by the Z-network parameters and desired bandwidth of each controller without a gain tuning process.