• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.613-622
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• 2013

In this paper, an inductive clamping class-E power amplifier has been tested for wireless power transmission at ISM band, 13.56 MHz. The implemented power amplifier is designed to operate stably without destroying power transistor in wireless power transmission system which basically keeps not to align between a transmitting antenna and a receiving antenna. The power amplifier is also designed to enhance harmonic filtering characteristic. The amplifier was tested with a DC supply voltage of 28 V and input power of 25 dBm at 13.56 MHz. The test results show the output power level of 43 dBm, the difference power level between fundamental frequency and second harmonic frequency of more than 55 dBc, the dc current consumption of 830 mA, and the high power-added efficiency of 85 %. Finally, the implemented power amplifier operated normally with 830 mA DC current consumption from 28 V source when the two antennas were aligned, and the power transmission was successful. But when the two antennas were not aligned, its DC current consumption automatically decreased down to 420 mA to protect the switching transistor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1343-1351
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• 2010

In this paper, a novel patch antenna based on the metamaterial CRLH(Composite Right- and Left-Handed) structure is designed, implemented, and measured. Contrary to the standard microstrip patch's fundamental resonance mode of half-wavelength or its positive multiple, the proposed antenna shows the in-phase electric field over the entire antenna. The proposed antenna has a desired omni-directional field pattern which is typical characteristic of $\lambda/4$ monopole antenna, and also shows the merit of low profile. HFSS(High Frequency Structure Simulator) of Ansoft which is based on the FEM(Finite Element Method) is used to simulate the proposed antenna. FR-4 substrate of thickness 1.6 mm and relative permitivity 4.4 is used for the proposed antenna implementation. The implemented antenna showed VSWR (Voltage Standarding Wave Ratio)$\leq$2 for the frequency band from 2.63 GHz to 2.655 GHz which is used for S-DMB (Satellite-Digital Multimedia Broadcasting) service. And measured peak gain and efficiency are 2.65 dBi and 81.14 %, respectively.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.3
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• pp.195-201
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• 2016

Eddy current testing (ECT) is commonly applied for the inspection of automated production lines of metallic products, because it has a high inspection speed and a reasonable price. When ECT is applied for the inspection of a metallic object having an uneven target surface, such as the spline gear of a spline shaft, it is difficult to distinguish between the original signal obtained from the sensor and the signal generated by a defect because of the relatively large surface signals having similar frequency distributions. To facilitate the detection of defect signals from the spline gear, implementation of high-order filters is essential, so that the fault signals can be distinguished from the surrounding noise signals, and simultaneously, the pass-band of the filter can be adjusted according to the status of each production line and the object to be inspected. We will examine the infinite impulse filters (IIR filters) available for implementing an advanced filter for ECT, and attempt to detect the flaw signals through optimization of system design parameters for detecting the signals at the system level.

• Korean Journal of Heritage: History & Science
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• v.44 no.4
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• pp.86-111
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• 2011

Wan is a tableware in which boiled rice or soup, side dish are put, and it is a representative model which shows the development of personal tableware. From the establishing period of Hanseong Baekje, the form of wan which is Jung-do Style(中島式) Plain Pottery of previous period Proto-Three Kingdoms Period was succeeded to, but wan is produced and used as a wan baked in the kiln, which is far development of the producing technique including hardness and clay. By and large, the size of $0.3{\sim}0.4{\ell}$ was the majority and the production technique of wan which used carefully selected soft quality clay are largely confirmed to be two methods which are, first, basic method by which on a clay tablet on the rotating table, clay band is accumulated and moulding is finished, and second, the new method which had the same basic moulding as that of basic method but in the last stage takes wan off the rotating table and reverse it to trim the bottom and remove the angle of flat bottom. The former, basic production method is the classical production method since wan of Jung-do Style Plain Pottery and wan was produced and used for all periods of Hanseong Baekje. On the other hand, the latter is the production method obtained through form imitation of China made porcelain flowed into through interchange between Baekje and China, and through comparison with Chinese chronogram material it is estimated to have been produced and used after middle of 4th century. Therefore it can be known that the Baekje people's demand for China made articles was big and imitation pottery was produced and used with Baekje pottery. In addition, bowl with outward mouth are confirmed in multiple number in Lakrang(樂浪) pottery wan and it is assumed that wan was the form produced under the influence.

• Journal of KIISE:Information Networking
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• v.31 no.4
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• pp.375-383
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• 2004

As wireless mobile networks have been widely adopted due to their convenience for deployment, the research for improving their performance has been actively conducted. Since their throughput is restrained by the packet corruption rate not by congestion as in wired networks, however, network simulations for performance evaluation need to select the appropriate wireless channel model representing the behavior of propagation errors for the evaluated channel. The selection of the right model should depend on various factors such as the adopted frequency band, the level of signal power, the existence of obstacles against signal propagation, the sensitivity of protocols to bit errors, and etc. This paper analyzes 10-day bit traces collected from real sensor channels exhibiting the high bit error rate to determine a suitable sensor channel model. For selection, it also evaluates the performance of two error recovery algorithms such as a link layer FEC algorithm and three TCPs (Tahoe, Reno, and Vegas) over several channel models. The comparison analysis shows that CM(Chaotic Map) model predicts 3-time less BER variance and 10-time larger PER(Packet Error Rate) than traces while these differences between the other models and traces are larger than 10-time. The simulation experiments, furthermore, prove that CM model evaluates the performance of these algorithms over sensor channels with the precision at least 10-time more accurate than any other models.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1156-1163
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• 2006

This paper presents an ultra wideband(UWB) direct conversion mixer for IEEE 802.15.3a applications with simulation and measurement results. Since the direct conversion mixing causes dc-offset and even-order distortion, the proposed mixer adopts an anti-parallel diode pairs(APDPs) to solve these problems. The proposed mixer consists of an in-phase wilkinson power divider over $3.1{\sim}4.8GHz$, a wideband $45^{\circ}$ power divider over $1.5{\sim}2.4GHz$, and miniatured band pass filters(BPFs) for RF-LO isolations. The conversion loss is optimized with impedance matchings between APDPs and wideband components. The measured mixer shows the conversion loss of 13.5 dB, input third-order intercept-point($IIP_3$) of 7 dBm, and 1-dB gam compression point($P_{1dB}$) of -4 dBm. Quadrature(I/Q) outputs have the magnitude difference of about 1 dB and phase difference of ${\pm}3^{\circ}$.

• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2004.03a
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• pp.389-397
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• 2004

본 연구는 GIS를 이용하여 아파트 단지의 UHF대역의 전파장애에 대한 예측모델을 제시한다. 전파예측모델은 기지국 및 중계기 위치설계와 전파음영지역 결정 등 무선네트워크 서비스에 결정적으로 활용된다 기존의 전파예측모델은 한국지형요소나 3차원 공간기술이 반영되지 않고 외국지형기반의 2차원적인 접근으로 개발되어 있다. 특히 많은 사람이 거주하는 아파트단지에 대해서는 고려가 되어 있지 않은 실정이며, 마치 아파트 단지가 일반 건물로 취급되어 전파환경 요소로 분류되지 않은 상태이다. 그리고 전파관리자가 기존 전파 예측모델을 이용한 무선네트워크 설계 및 운용등에 있어 정확한 의사결정지원에 어려움이 많다. 본 연구는 이러한 한계와 문제점을 해결하기 위해서 아파트 단지의 전파에 대한 영향을 3차원 공간밀집, 건물높이, 전파의 전송방향에 대한 건물배치등 3가지 요소로 분류하고 GIS 도구로 그 요소들을 분석하였다. 그 결과로 상관과 회귀분석등 정량적인 방법으로 평가하여 아파트 전파예측모델(GARP)을 개발하여 다음의 결과를 얻었다. 첫째, 아파트 단지가 UHF 대역의 전파에 대한 영향은 전파진행방향성이 57%, 공간밀집이 30%, 건물높이가 13%의 순으로 나타났다. 둘째, 본 연구에서 개발된 아파트 모델은 기존 모델에 비해 평균 6.3dBm, 최소 2.15 ～ 최대 12.48dBm의 개선 효과가 있다. 셋째, 급속히 확산되는 도시 개발에 3차원 공간상에서 전파예측모델을 시뮬레이션하여 전파의 영향을 예측할 수 있으며, 대단지 아파트 건설과 전파환경영향평가의 기초정보 수집에 활용될 수 있다. 본 연구는 GARP모델과 GIS 가시권 분석기능을 이용하여 실제 지형공간상에서 전파경로 손실치를 도시화함으로써 전파관리자가 무선서비스지역 설계, 전파음영지역 판단, 최적 중계기와 기지국 위치 선정에 기여할 것으로 판단된다.하지 않은 지역과 서로 다른 분광특성을 나타내므로 별도의 Segment를 형성하게 된다. 따라서 임상도의 경계선으로부터 획득된 Super-Object의 분광반사 값과 그 안에서 형성된 Sub-Object의 분광반사값의 차이를 이용하여 임상도의 갱신을 위한 변화지역을 탐지하였다.라서 획득한 시추코아에 대해서도 각 연구기관이 전 구간에 대해 동일하게 25%의 소유권을 가지고 있다. ？스굴 시추사업은 2008년까지 수행될 계획이며, 시추작업은 2005년까지 완료될 계획이다. 연구 진행과 관련하여, 공동연구의 명분을 높이고 분석의 효율성을 높이기 위해서 시료채취 및 기초자료 획득은 4개국의 연구원이 모여 공동으로 수행한 후의 결과물을 서로 공유하고, 자세한 전문분야 연구는 각 국의 대표기관이 독립적으로 수행하는 방식을 택하였다 ？스굴에 대한 제1차 시추작업은 2004년 3월 말에 실시하였다. 시추작업 결과, 약 80m의 시추 코아가 성공적으로 회수되어 현재 러시아 이르쿠츠크 지구화학연구소에 보관중이다. 이 시추코아는 2004년 8월 중순경에 4개국 연구팀원들에 의해 공동으로 기재된 후에 분할될 계획이다. 분할된 시료는 국내로 운반되어 다양한 전문분야별 연구에 이용될 것이다. 한편, 제2차 시추작업은 2004년 12월에서 2005년 2월 사이에 실시될 계획이다. 수백만년에 이르는 장기간에 걸쳐 지구환경변화 기록이 보존되어 있는 ？스굴호에 대한 시추사업은 후기 신생대 동안 유라시아 대륙 중부에서 일어난 지구환경 및 기후변화를 이해함과 동시에 이러한 변화가 육상생태계 및 지표지질환경에 미친 영향을 이해하는데 크게 기여할 것이다.lieve in safety with Radioactivity wastes control for harmony with Environment.d by the experiments under vari