• 한국컴퓨터정보학회논문지
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• 제22권12호
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• pp.131-136
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• 2017

PLM(Product Lifecycle Management) is an information management system that can integrate data, processes, business systems and human resources throughout the enterprise. BOM(Bills Of Material) is key data for designing, purchasing materials, manufacturing planning and management, which is basic for product development throughout the product life cycle. In this paper, we propose the efficient system to increase the data loading speed and the processing speed when using such large BOM data. We present the performance and usability of IMDG (In Memory Data Grid) for data processing when loading large amounts of data. In the UI, using the pure web grid of JavaScript instead of the existing data loading method can be improve performance of data managing.

• 정보처리학회논문지D
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• 제14D권7호
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• pp.733-742
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• 2007

데이터 스트림이란, 빠른 속도로 지속적으로 생성되는 무한한 크기의 방대한 양의 데이터 집합으로 정의된다. 무한한 데이터 스트림에 비해 주어진 메모리 공간은 유한하게 한정되어 있어, 이러한 제약조건을 충족시키는 범위 내에서 일정 한도내의 정확도 오차를 허용하기도 한다. 또한, 변화하는 데이터 스트림 내의 최신 클러스터를 찾기 위해서는 데이터 객체의 저장없이 오래된 데이터 스트림 내의 정보들을 비중을 감소시킬 수 있어야 한다. 본 연구에서는 데이터 스트림 분석을 위한 데이터 스트림 격자 기반 클러스터링 기법을 제시한다. 주어진 초기 격자셀에 대해, 데이터 객체의 빈도가 높은 범위를 반복적으로 보다 작은 크기의 격자셀로 분할하여 최소 크기의 격자셀, 단위 격자셀을 생성한다. 격자 셀에서는 데이터 객체들의 분포에 대한 통계값만을 저장하여, 기존의 클러스터링 기법에 비해 데이터 객체에 대한 탐색없이 효율적으로 클러스터를 찾을 수 있다. 또한, 가용 메모리 공간에 따라 단위 격자셀의 크기를 조절하여 클러스터의 정확도를 최대화할 수 있어, 주어진 메모리 공간에 맞게 적응적으로 성능을 조절할 수 있다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 품질경영학회지
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• 제49권2호
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• pp.201-211
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• 2021

Purpose: This paper proposes a density adaptive grid algorithm for the k-NN regression model to reduce the computation time for large datasets without significant prediction accuracy loss. Methods: The proposed method utilizes the concept of the grid with centroid to reduce the number of reference data points so that the required computation time is much reduced. Since the grid generation process in this paper is based on quantiles of original variables, the proposed method can fully reflect the density information of the original reference data set. Results: Using five real-life datasets, the proposed k-NN regression model is compared with the original k-NN regression model. The results show that the proposed density adaptive grid-based k-NN regression model is superior to the original k-NN regression in terms of data reduction ratio and time efficiency ratio, and provides a similar prediction error if the appropriate number of grids is selected. Conclusion: The proposed density adaptive grid algorithm for the k-NN regression model is a simple and effective model which can help avoid a large loss of prediction accuracy with faster execution speed and fewer memory requirements during the testing phase.

• 정보처리학회논문지A
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• 제11A권4호
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• pp.267-276
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• 2004

자동배치/배선 시스템의 배선영역 모델링 방법은 그리드와 논 그리드 방식을 사용하고 있다. 그리드 방식은 PCB상에 전기적, 물리적 요소들이 적다할지라도 보드와 그리드의 크기에 제약을 받기 때문에 메모리가 많아지게 되어 자동배치/배선 속도를 감소시키는 단점을 가지고 있다. 논 그리드 방식인 형상기반 방식은 영역처리 방식을 사용하므로 형상들을 메모리에 각각의 객체로서 존재시키며, 이들 객체는 고유의 데이터 크기를 갖기 때문에 메모리가 상당히 적게 소요된다. 그러므로 본 논문에서는 단일 원점에서 여러 목적지에 가장 빠르게 도달 할 수 있는 최단 경로 문제를 해결하는 경매 알고리즘을 적용하여 형상기반 방식에 의하여 메모리 낭비 없이 빠른 속도로 자동배치/배선할 수 있는 PCB 자동배치/배선 시스템을 개발하였다. 또한 본 시스템은 이와 같은 방식을 이용하여 PC에서 사용할 수 있도록 IBM Pentium 컴퓨터의 Windows 환경에서 Visual C++언어로 개발하였다.

• 한국정보통신학회논문지
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• 제18권1호
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• pp.103-108
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• 2014

스마트폰과 같은 휴대용 기기에서 많이 사용되는 플래쉬 메모리는 비휘발성 저장장치로 작은 크기에 대용량 데이터를 안정적으로 저장할 수 있는 장점을 가지고 있다. 플래쉬 메모리에 저장된 대용량 데이터에 대한 질의 연산을 효율적으로 처리하기 위하여 색인을 사용해야 한다. 그러나 플래쉬 메모리는 쓰기 연산의 속도가 느리고 덮어쓰기 연산을 지원하지 않기 때문에 기존의 색인을 평가하고 개선점을 파악할 필요가 있다. 이 논문에서는 플래쉬 메모리에 적용한 공간분할 기법의 공간 색인에 대한 성능을 평가한다. 이를 위하여 고정그리드파일을 구현하여 다양한 환경에서 질의 연산과 변경 연산의 평균 연산 수행 속도를 측정한다. 그리고 자기디스크 저장장치에서의 수행속도와 비교한다.

• 한국멀티미디어학회논문지
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• 제19권2호
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• pp.411-417
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• 2016

Since the development of Graphic Processing Unit (GPU) in 1999, the development speed of GPUs has become much faster than that of CPUs and currently, the computational power of GPUs exceeds CPUs dozens and hundreds times in terms of decimal calculations and costs much less. Owing to recent technological development of hardwares, general-purpose computing and utilization using GPUs are on the rise. Thus, in this paper, we have identified the elements to be considered for the Smart Grid Security. Focusing on a Performance Improvement of the Basic Algorithm for the Stateful Inspection to Detect DDoS Attacks using CUDA. In the program, we compared the search speeds of GPU against CPU while they search for the suffix trees. For the computation, the system constraints and specifications were made identical during the experiment. We were able to understand from the results of the experiment that the problem-solving capability improves when GPU is used. The other finding was that performance of the system had been enhanced when shared memory was used explicitly instead of a global memory as the volume of data became larger.

• ETRI Journal
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• 제42권4호
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• pp.608-618
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• 2020

We present a novel GPU-based ray-casting algorithm for volume rendering of unstructured grid data. Our volume rendering system uses a ray-casting method that guarantees accurate rendering results. We also employ the per-pixel intersection list concept in the Bunyk algorithm to guarantee an accurate result for non-convex meshes. For efficient memory access for the lists on the GPU, we represent the intersection lists for all faces as an array with our novel construction algorithm. With the intersection lists, we perform ray-casting on a GPU, and a GPU thread handles each ray. To increase ray-coherency in a thread block and improve memory access efficiency, we extend a prior image-tile-based work distribution method to fit modern GPU architectures. We also show that a prior approach using a per-thread local buffer to reduce redundant computation is not appropriate for modern GPU architectures. Instead, we take an on-demand calculation strategy that achieves better performance even though it allows duplicate computations. We applied our method to three unstructured grid datasets with different characteristics. With a GPU, our method achieved up to 36.5 times higher performance for the ray-casting process and 19.7 times higher performance for the whole volume rendering process compared with the Bunyk algorithm using a CPU core. Also, our approach showed up to 8.2 times higher performance than a GPU-based cell projection method while generating more accurate rendering results. These results demonstrate the efficiency and accuracy of our method.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 정보처리학회논문지A
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• 제13A권6호
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• pp.511-516
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• 2006

데이터 그리드는 대용량의 데이터 어플리케이션 처리를 위해 지리적으로 분산되어 있는 저장 자원을 제공한다. 대용량을 처리해야 하는 데이터 그리드 환경에서는 기존 웹 캐싱 정책이나 가상 메모리 캐쉬 교체 정책과는 다른 파일 교체 정책이 필요하다. LRU(Least Recently Used)나 LCB-K(Least Cost Beneficial based on K), EBR(Economic-based cache replacement), LVCT(Least Value-based on Caching Time) 같은 기존의 파일 교체 전략은 파일 교체를 위해 추가적인 자원이 필요하거나 미래를 예측해야한다. 본 논문은 이를 해결하기 위해 파일의 크기에 기반하여 파일 교체를 수행하는 SBR-k(Sized-based replacement-k)을 제안한다. 성능평가 결과 제안한 정책이 기존의 정책보다 더 나은 성능을 나타낸다는 것을 확인하였다.