• The Journal of Asian Finance, Economics and Business
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• 제7권10호
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• pp.543-553
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• 2020

This paper examines the effect of COVID-19 pandemic on the Philippine stock exchange, peso-dollar rate and retail price of diesel using robust least squares regression and vector autoregression (VAR). The robust least squares regression using MM-estimation method concluded that COVID-19 daily infection has negative and statistically significant effect on the Philippine stock exchange index, peso-dollar exchange rate and retail pump price of diesel. This is consistent with the results of correlation diagnostics. As for the VAR model, the lag values of the independent variable disclose significance in explaining the Philippine stock exchange index, peso-dollar exchange rate and retail pump price of diesel. Moreover, in the short run, the impulse response function confirmed relative effect of COVID-19 daily infections and the variance decomposition divulge that COVID-19 daily infections have accounted for only minor portion in explaining fluctuations of the Philippine stock exchange index, peso-dollar exchange and retail pump price of diesel. In the long term, the influence levels off. The Granger causality test suggests that COVID-19 daily infections cause changes in the Philippine stock exchange index and peso-dollar exchange rate in the short run. However, COVID-19 infection has no causal link with retail pump price of diesel.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• ETRI Journal
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• 제33권5호
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• 한국음향학회지
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• 제20권1호
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• pp.43-49
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• 2001

EVRC (Enhanced Variable Rate Codec)는 북미 및 우리 나라 CDMA 디지털 셀룰러 시스템에 채택되었으며 8kbps의 전송률에서 우수한 성능을 갖는 부호화기이다. 본 논문에서는 복잡한 알고리듬으로 인해 많은 계산량을 갖는 EVRC 부호화기를 성능 저하 없이 고속으로 구현할 수 있는 알고리듬을 제시한다. 제안된 고속 알고리듬에서는 효율적인 피치 검색과 고정 코드북 탐색 과정이 구현되는데, 고정 코드북 탐색 과정에서는 펄스 위치 조합의 수를 제한하는 방법과 줄여진 임펄스 응답을 사용하여 연산량을 기존의 방법의 70％ 정도로 감소시킨다. 주관적인 음질 평가를 통해 제안된 고속 EVRC 알고리듬이 기존의 방법에 비해 적은 계산량에 구현되지만 음질의 저하는 초래하지 않는다는 것을 확인하였다.

• 센서학회지
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• 제19권6호
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• pp.490-496
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• 2010

In this study, in order to overcome the weakness of acoustic field analysis which is generally used for ultrasonic probe performance evaluation, automatic acoustic field measurement system and evaluation parameters were proposed. The comparisons between acoustic field simulation and measured acoustic distribution data of normal and abnormal channels were conducted to evaluate the availability of proposed system and evaluation parameters. First, the impulse response characteristic of sample probe was investigated to classify the normal elements and abnormal elements. And then, normal channels and abnormal channels with abnormal element were chosen. The suggested 12 evaluation parameters were calculated using the acoustic fields of these channels. The availability of proposed automatic acoustic field measurement system and evaluation parameters was confirmed. And the performance evaluation of ultrasonic probe using acoustic field analysis could be easier and faster.

• 전력전자학회논문지
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• 제12권3호
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• pp.241-247
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• 2007

LLC 하프브리지 다중 출력용 컨버터의 보조 출력부와 같이, 펄스 전압을 입력으로 갖는 PWM 컨버터에서는 출력 정전압 제어를 위하여 스위치의 턴 온 제어 방식을 필요로 한다. 본 논문에서는 전류 불연속 모드로 동작하는 벅 컨버터의 새로운 도통시간 턴 온 제어방식에 대하여 논하였다. 제안된 LEM 제어 방식의 PWM 동작 원리를 설명하였으며, 임펄스 응답 이론을 근거로 인덕터 전류의 소신호 주파수 응답 특성을 고찰하였다. 또한 60인치 PDP 어드레스용 100W급 파워 모듈에 적용함으로서 제안된 제어 방식의 타당성을 검증하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.585-591
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• 2000

The wavelet transform is the most recent technique for processing signals with time-varying spectra. In this paper, the wavelet transform is utilized to improved the assessment and multi-resolution analysis of acoustic emission signals generating in partial discharge. This paper especially deals with the assessment of process statistical parameter using the features extracted from the wavelet coefficients of measured acoustic emission signals in case of applied voltage 20[kv]. Since the parameter assessment using all wavelet coefficients will often turn out leads to inefficient or inaccurate results, we selected that level-3 stage of multi decomposition in discrete wavelet transform. We applied FIR(Finite Impulse Response)digital filter algorithm in discrete to suppression for random noise. The white noise be included high frequency component denoised as decomposition of discrete wavelet transform level-3. We make use of the feature extraction parameter namely, maximum value of acoustic emission signal, average value, dispersion, skewness, kurtosis, etc. The effectiveness of this new method has been verified on ability a diagnosis transformer go through feature extraction in stage of acting(the early period, the last period) .

• 한국군사과학기술학회지
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• 제24권5호
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• pp.475-481
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• 2021

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.

• Journal of Information Processing Systems
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• 제15권2호
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.