• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1803-1811
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• 2001

In this paper, Forward Error Correction(FEC) that is satisfied with ITU-T Recommendation J.83, Annex B(North American Data Over Cable Service Interface Specifications(DOCSIS) for Multimedia Cable Network System(MCNS)) is analyzed. The FEC consist of Reed-Solomon(RS) layer, interleaving layer, randomization layer, and trellis coded modulation(TCM) layer. The effects of quantization of input symbol and of trace-back depth in the Viterbi decoder are simulated over AWGN channels.