• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2024년도 춘계학술발표대회
• /
• pp.415-418
• /
• 2024

본 논문에서는 TFHE(Fast Homomorphic Encryption over the Torus) 파라미터의 중요성과 그파라미터가 동형암호 연산의 성능에 미치는 영향을 다룬다. 본 연구는 TFHE의 핵심 구성 요소인 TLWE, TRLWE, TRGSW 샘플의 파라미터 설정이 어떻게 보안 수준, 정확도, 처리 속도에 영향을 미치는지 분석한다. 이를 통해, 정확도와 처리 속도 같은 성능과 보안 수준 사이의 균형을 이루기 위한 파라미터 조정의 중요성을 강조하고, TFHE 파라미터를 사용하는 방법에 대한 구체적인 가이드라인을 제공한다. 본 논문은 동형암호 기술의 효율성을 극대화하고, 보다 안전하고 효율적인 데이터 처리 방법을 개발하는 데 기여할 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권2호
• /
• pp.167-173
• /
• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권3호
• /
• pp.360-369
• /
• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of Korean Vacuum Science & Technology
• /
• 제4권3호
• /
• pp.73-77
• /
• 2000

Single crystal and polycrystalline Si thin films were doped with phosphorus by a 2-zone diffusion method to develop the low-resistivity polycrystalline Si electrode for a hemispherical grain. Solid phosphorus source was used in order to achieve uniformly and highly doped surface region of polycrystalline Si films having rough surface morphology. In case of 2-zone diffusion method, it is proved that the heavy doping near the surface area can be achieved even at a relatively low temperature. SIMS analysis revealed that phosphorus doping concentration in case of using solid P as a doping source was about 50 times as that of phosphine source at 750$^{\circ}C$. Also, ASR analysis revealed that the carrier concentration was about 50 times as that of phosphine. In order to evaluate the electrical characteristics of doped polycrystalline Si films for semiconductor devices, MOS capacitors were fabricated to measure capacitance of polycrystalline Si films. In ${\pm}$2 V measuring condition, Si films, doped with solid source, have 8% higher $C_{min}$ than that of unadditional doped Si films and 3% higher $C_{min}$ than that of Si films doped with $PH_3$ source. The leakage current of these films was a few fA/${\mu}m^2$. As a result, a 2-zone diffusion method is suggested as an effective method to achieve highly doped polycrystalline Si films even at low temperature.

• 한국정보처리학회:학술대회논문집
• /
• 한국정보처리학회 2024년도 춘계학술발표대회
• /
• pp.666-669
• /
• 2024

연합학습은 원본 데이터를 공유하지 않고 모델을 학습할 수 있는 각광받는 프라이버시를 위한 학습방법론이다. 이를 위해 참여자의 데이터를 수집하는 대신, 데이터를 인공지능 모델 학습의 요소들(가중치, 기울기 등)로 변환한 뒤, 이를 공유한다. 이러한 강점에 더해 기존 연합학습을 개선하는 방법론들이 추가적으로 연구되고 있다. 기존 연합학습은 모델 가중치를 평균내는 것으로 참여자 간에 동일한 모델 구조를 강요하기 때문에, 참여자 별로 자신의 환경에 알맞은 모델 구조를 사용하기 어렵다. 이를 해결하기 위해 지식 증류 기반의 연합학습 방법(Knowledge Distillation-based Federated Learning)으로 서로 다른 모델 구조를 가질 수 있도록(Model Heterogenousity) 하는 방법이 제시되고 있다. 연합학습은 여러 참여자가 연합하기 때문에 일부 악의적인 참여자로 인한 모델 포이즈닝 공격에 취약하다. 수많은 연구들이 기존 가중치를 기반으로한 연합학습에서의 위협을 연구하였지만, 지식 증류 기반의 연합학습에서는 이러한 위협에 대한 조사가 부족하다. 본 연구에서는 최초로 지식 증류 기반의 연합학습에서의 모델 성능 하락 공격에 대한 위협을 실체화하고자 한다. 이를 위해 우리는 GMA(Gaussian-based Model Poisoning Attack)과 SMA(Sign-Flip based Model Poisoning Attack)을 제안한다. 결과적으로 우리가 제안한 공격 방법은 실험에서 최신 학습 기법에 대해 평균적으로 모델 정확도를 83.43%에서 무작위 추론에 가깝게 떨어뜨리는 것으로 공격 성능을 입증하였다. 우리는 지식 증류 기반의 연합학습의 강건성을 평가하기 위해, 새로운 공격 방법을 제안하였고, 이를통해 현재 지식 증류 기반의 연합학습이 악의적인 공격자에 의한 모델 성능 하락 공격에 취약한 것을 보였다. 우리는 방대한 실험을 통해 제안하는 방법의 성능을 입증하고, 결과적으로 강건성을 높이기 위한 많은 방어 연구가 필요함을 시사한다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권2호
• /
• pp.204-209
• /
• 2016

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권2호
• /
• pp.191-197
• /
• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권5호
• /
• pp.566-571
• /
• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권3호
• /
• pp.370-376
• /
• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
• /
• pp.445-448
• /
• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.