• Applied Chemistry for Engineering
• /
• v.23 no.2
• /
• pp.169-175
• /
• 2012

In the study, the effects of $130{\sim}150^{\circ}C$ annealing condition and 1~10 wt% isopropylphenyl diphenyl phosphate (IPPP) on crystallization behavior and flame retardancy of a full name (PLA) film were determined. The crystallization kinetics of PLA films with adding 1, 5, and 10 wt% IPPP at $140^{\circ}C$ were higher than those at 130 and $150^{\circ}C$. The average crystallinity and crystallite size of PLA film with 1 wt% IPPP were 21.3% and 24.8 nm, respectively. With an increasing IPPP content, the crystallinity of PLA film increased and the crystallite size decreased. The burning rate lowered with an increasing IPPP content as well.

• Journal of Positioning, Navigation, and Timing
• /
• v.10 no.4
• /
• pp.379-385
• /
• 2021

In order to synchronize a remote system time to the reference time like Coordinated Universal Time (UTC), it is required to compare the time difference between the two clocks. GNSS Precise Point Positioning (PPP) is one of the most general geodetic positioning methods and can be used for time and frequency transfer applications which require more precise time comparison performance than GNSS code. However, the PPP technique has a main drawback of day-boundary discontinuity which comes from the PPP model that the code measurements are applied to resolve the floating carrier-phase ambiguities. The Integer PPP (IPPP) technique is one of the methods which has been studied to compensate the day-boundary discontinuities exited in the conventional PPP. In this paper, we investigate the time and frequency capabilities of PPP and IPPP by using the measurement data obtained from two time transfer receivers which are closely located and using common reference 1 Pulse Per Second (PPS) and RF signals. From the experiment, it is investigated that the IPPP method can effectively compensate the day-boundary discontinuities without producing frequency offset. However, the PPP method can generating frequency offset which can severely degrade the time comparison performance with long-term period data.

• The Journal of the Korea Contents Association
• /
• v.9 no.2
• /
• pp.27-35
• /
• 2009

In this paper, we present result of embedded system based H.264/SVC decoder circuit design and system implementation. To deal with the standardized H.264/SVC functionalities, the presented SVC decoder system is consist of hardware engine design and software with ARM core processor. In order to improve the feasibility and applicability, and reduce the decoder complexity, the implemented system is constructed with only the consideration of IPPP structure scalability without using the full B-picture architecture. Finally, we will show the decoding image result using the designed H.264/SVC decoder system.

• The Journal of the Korea Contents Association
• /
• v.9 no.3
• /
• pp.20-27
• /
• 2009

H.264/AVC video coding standard adapting a rate-distortion optimization technique to select the best coding mode with multi reference frames for each macroblock gets a higher coding efficiency than those of previous video coding standards but the computational complexity increases drastically. Therefore, many fast mode decision algorithms are proposed to reduce the computational complexity. Among them, we propose a fast intra mode decision algorithm based on directional information of I4MB. The proposed algorithm achieves consistent time saving about 15% in IPPP sequences and 44% in all I frame sequences with negligible loss in PSNR and small increment of bit rate compared with that of JM11.0.

• The Journal of the Korea Contents Association
• /
• v.9 no.3
• /
• pp.9-19
• /
• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2010.11a
• /
• pp.96-99
• /
• 2010

H.264/AVC 부호화 표준은 영상의 특성을 반영하기 위해 $16{\times}16$부터 $4{\times}4$ 크기의 가변적인 블록을 이용하여 부호화 효율을 높인다. 하지만 이로 인해 부호기의 복잡도가 증가된다. 부호기 복잡도를 증가시키는 여러 요인 중, H.264/AVC의 모드 결정은 부호기의 복잡도를 증가시키는 주요인이다. 본 논문에서는 IPPP구조에서 비트율 왜곡값을 이용하여 고속으로 매크로블록의 모드를 결정하는 방법을 제안한다. 인트라 화면에서의 인트라 $4{\times}4$, 인트라 $16{\times}16$의 비트율 왜곡 평균값으로 영상에 적응적인 최대 임계값과 최소 임계값을 결정한다. 다음, $16{\times}16$, $16{\times}8$, $8{\times}16$ 인터 모드의 비트율 왜곡값이 최대 임계값과 최소 임계값으로 분할한 범위 중 어느 곳에 해당하는지를 살펴보고, 이에 따라 인트라 모드 결정 단계를 선택적으로 결정한다. 제안하는 알고리즘은 기존의 H.264/AVC에 비해 부호화 효율의 큰 감소 없이 평균 27.42%의 부호화 시간을 감소시켰다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2011.07a
• /
• pp.348-351
• /
• 2011

가변적인 블록을 이용하는 H.264/AVC 인터 화면에서의 모드 결정 방법은 $16{\times}16$부터 $P8{\times}8$ 모드까지 인터 모드에 대해 비트율 왜곡값을 계산 한 뒤 공간적 상관도를 고려하기 위해 인트라 $4{\times}4$와 인트라 $16{\times}16$ 모드까지 비트율 왜곡값을 계산하고, 계산된 비트율 왜곡값 중 가장 작은 값을 갖는 모드를 최종 모드로 선택한다. 하지만 이러한 과정으로 부호기의 복잡도는 증가한다. 복잡도를 감소시키기 위해 본 논문에서는 IPPP구조에서의 인터 모드와 인트라 모드의 특징을 이용하여 고속 부호화를 제안한다. 제안하는 알고리즘은 인터 모드에 대해서 최적 모드를 결정하기 위한 비트율 왜곡값의 상관도와 시간 상관도를 이용하고, 인트라 모드에 대해서는 인트라 화면 내에서의 각 인트라 모드에 대한 최대 최소 임계값을 이용하여, 발생확률이 낮은 인터와 인트라 모드의 활성화 여부를 결정한다. 본 알고리즘의 적용 범위는 상대적으로 인터 화면에서 발생 빈도가 낮은 $16{\times}8$, $8{\times}16$, $P8{\times}8$와, 인트라 $4{\times}4$, 인트라 $16{\times}16$ 모드이다. 제안하는 알고리즘은 기존의 H.264/AVC에 비해 1.36% 비트가 증가 했고, PSNR은 0.06dB 감소했다. 즉, 부호화 효율의 큰 감소 없이 평균 42.58%의 부호화 시간을 감소시켰다.

• ETRI Journal
• /
• v.28 no.6
• /
• pp.721-731
• /
• 2006

A fast intra skip detection algorithm based on the ratedistortion (RD) cost for an inter frame (P-slices) is proposed for H.264/AVC video encoding. In the H.264/AVC coding standard, a robust rate-distortion optimization technique is used to select the best coding mode and reference frame for each macroblock (MB). There are three types of intra predictions according to profiles. These are $16{\times}16$ and $4{\times}4$ intra predictions for luminance and an $8{\times}8$ intra prediction for chroma. For the high profile, an $8{\times}8$ intra prediction has been added for luminance. The $4{\times}4$ prediction mode has 9 prediction directions with 4 directions for $16{\times}16$ and $8{\times}8$ luma, and $8{\times}8$ chrominance. In addition to the inter mode search procedure, an intra mode search causes a significant increase in the complexity and computational load for an inter frame. To reduce the computational load of the intra mode search at the inter frame, the RD costs of the neighborhood MBs for the current MB are used and we propose an adaptive thresholding scheme for the intra skip extraction. We verified the performance of the proposed scheme through comparative analysis of experimental results using joint model reference software. The overall encoding time was reduced up to 32% for the IPPP sequence type and 35% for the IBBPBBP sequence type.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.01a
• /
• pp.142-147
• /
• 2009

The recent H.264/AVC video coding standard provides a higher coding efficiency than previous standards. H.264/AVC achieves a bit rate saving of more than 50 % with many new technologies, but it is computationally complex. Most of fast mode decision algorithms have focused on Baseline profile of H.264/AVC. In this paper, a fast block mode decision scheme for P- slices in High profile is proposed to reduce the computational complexity for H.264/AVC because the High profile is useful for broadcasting and storage applications. To reduce the block mode decision complexity in P- pictures of High profile, we use the SAD value after $16{\times}16$ block motion estimation. This SAD value is used for the classification feature to divide all block modes into some proper candidate block modes. The proposed algorithm shows average speed-up factors of 47.42 ${\sim}$ 67.04% for IPPP sequences.

• Journal of Broadcast Engineering
• /
• v.9 no.3
• /
• pp.214-224
• /
• 2004

In this paper, an adaptive spatio-temporal predictive coding based on the H.264 is proposed for 3D immersive media encoding, such as 3D image processing, 3DTV, and 3D videoconferencing. First, we propose a spatio-temporal predictive coding using the same view and inter-view images for the two TPPP, IBBP GOP (group of picture) structures 4hat are different from the conventional simulcast method. Second, an 2D inter-view direct mode for the efficient prediction is proposed when the proposed spatio-temporal prediction uses the IBBP structure. The 2D inter-view direct mode is applied when the temporal direct mode in B(hi-Predictive) picture of the H.264 refers to an inter-view image, since the current temporal direct mode in the H.264 standard could no: be applied to the inter-view image. The proposed method is compared to the conventional simulcast method in terms of PSNR (peak signal to noise ratio) for the various 3D test video sequences. The proposed method shows better PSNR results than the conventional simulcast mode.