• International Journal of Advanced Culture Technology
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• v.10 no.2
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• pp.233-239
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• 2022

Recently, research is being conducted on the rapid service provision and reliability of the instance-based rather than the existing IP-based structure. Research is mainly conducted through Block cloud, a platform that combines service-centric networking (SCN) and blockchain. In addition, the Internet of Things network has been proposed as a fog computing environment in the structure of the existing cloud computing. Fog computing is an environment suitable for real-time information processing. In this paper, we propose a new Internet network structure based on fog computing that requires real-time for rapid processing of IoT services. The proposed system applies IoTA, the third-generation blockchain based on DAG, to the block cloud. In addition, we want to propose a basic model of the object block chain and check the application services of electric vehicles.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.859-861
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• 2001

VIA는 클러스터 또는 시스템 영역 네트워크를 위한 표준화된 사용자수준 통신 아키텍쳐이고, GFS는 LINUX 클러스터에서 사용할 수 있는 공유 락일 시스템이다. 클러스터 환경에서 GFS를 사용할 때 특별한 스토리지 네트워크가 설치되어 있지 않으면 GNBD를 사용한다. GNBD는 TCP/TP 상의 소켓을 기반으로 구현되어 있기 때문에, VIA를 사용하는 클러스터이더라도 VIA 하드웨어 상에서 TCP/IP 소켓을 통하여 GNBD를 작동시킨다. VIA와 같이 물리적 연결이 신뢰성이 높고 높은 수준의 기능을 제공하는 경우는 같은 클러스터 안에서 TCP/IP 프로토콜 스택을 사용할 필요가 없다. 본 논문은 VIA상에서 GNBD를 위한 고속 통신 계층(VCONN)을 제안하여, 동일한 VIA 하드웨어에서 지원되는 TCP/IP 모듈을 사용했을 때보다 읽기, 쓰기 성능을 각각 약 22%, 30% 향상시키는 방법을 소개한다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.6
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• pp.78-87
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• 2009

In this paper, we propose a new method of blocky artifacts measurement for IP based video service. In order to assess the quality of IP based video service, we classify degradation into blocking artifacts by network error or by transmission error. in order to assess blocking artifacts based on No-reference, we estimate blocky artifacts from network errors and image compression by calculating amount of difference between target block and neighbor blocks and error concealment algorithm in a video receiver. To ensure accuracy of proposed method, we compare our result to MOS data using SSCQE method. Experimental results show that the proposed algorithm is better than a conventional method by around 1.3.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.447-453
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• 2004

In this paper, we propose a new system to block harmful Internet information based on IP spoofing. The proposed system is located on a organization's internal network and monitors all outgoing traffic and lets all this traffic go outside. Once the proposed system detects a host's access to a harmful site, it sends the host a pseudo RST packet that pretends to be the response from the harmful site, and prevents the connection between the host and the harmful site. The proposed software system is installed on only a server, and need not be installed on user hosts at all. Thus we can maintain and upgrade the blocking system easily. The performance evaluation of the proposed system shows that it effectively blocks the access to the harmful sites. Since the proposed system is based on IP spoofing, it can be used badly as a hacking tool. Finally we propose some methods to eliminate this possibility.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.1-8
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• 2023

This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

• Clinical and Experimental Reproductive Medicine
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• v.30 no.4
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• pp.269-280
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• 2003

Objective: We reported the overcoming effect of $Ni^{2+}$ on the in vitro 2-cell block of mouse embryos. In this study, we aim to investigate whether $Ni^{2+}$ should induce intracellular $Ca^{2+}$ transient in the mouse embryos. Materials and Methods: Embryos were collected at post hCG 32hr from the oviduct of the ICR mouse and cultured in M2 medium omitted phenol red. Intracellular $Ca^{2+}$ was checked by using a confocal laser scanning microscope and fluo-3AM by using various intracellular $Ca^{2+}$ antagonists. Results: In 1mM $Ni^{2+}$ treated medium which contained $Ca^{2+}$(1.71mM), 75.7% of the embryos showed $[Ca^{2+}]i$ transient about 200 sec later. In the $Ca^{2+}$-free medium, 69.8% of the embryos showed $[Ca^{2+}]i$ transient. In U73122, phospholipaseC(PLC) inhibitor (5uM, 10min) pretreated group, 33.3% of the embryos showed $[Ca^{2+}]i$ transient. Heparine, inositol 1, 4, 5-triphosphate receptor(IP3R) antagonist preinjected embryos showed no response with 1mM $Ni^{2+}$. In danthrolene treatment, ryanodine receptor(RyR)-antagonist, 43% embryos showed $[Ca^{2+}]i$ transient but they showed delayed response about 340sec in the presence of $Ca^{2+}$. Conclusions: Summing up the above results, $Ni^{2+}$ seems to induce $Ca^{2+}$-release from the $Ca^{2+}$-store even in the $Ca^{2+}$-free medium. IP3 receptors of the mouse 2-cell embryos might have an essential role for the intracellular $Ca^{2+}$ increase by $Ni^{2+}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.267-276
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• 2009

Nowadays, numerous of valuable internet services are available not only for personal computer but also for mobile appliances in wireless network environment. Therefore, as the amount of contents is increased for those services, the storage limitation on mobile devices has became a significant issue. In this paper, we present a new block-level storage network protocol, iATA (Internet Advanced Technology Attachment) as a solution to the above problem. iATA is designed to transport ATA block-level data and command over the ubiquitous TCP/IP network. With iATA, a mobile appliance is able to access and control the ATA storage devices natively through network from anywhere and at anytime as if the storage devices is attached locally. We describe the concepts, design and diverse consideration of iATA protocol. Based on the benchmark experiments and application exploitation, we strongly believe that iATA as a light-weight protocol is efficient and cost-effective to be used as a storage network protocol on a resource limited device that utilizes common-off-the-shelf storage hardware and existing IP infrastructure.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.20-29
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• 2014

Recently, LTE is preparing to make a new leap forward LTE-A all over the world. As LTE privides high speed service, the role of mobile phones seems to change from voice to data service. According to Cisco, global mobile data traffic will increase nearly 11-fold between 2013 and 2018. Mobile video traffic will reach 75% by 2018 from 66% in 2013 in Korea. However, voice service is still the most important role of mobile phones. Thus, controllability of throughput and low BLER is indispensable for high-quality VoIP service among various type of traffic. Although the maximum AMR-WB, 23.85 Kbps is sufficient to a VoIP call, it is difficult for the LTE which can provide tens to hundreds of MB/s may not keep the certain level VoIP QoS especially in the cell-edge area. This paper proposes a new scheduling algorithm in order to improve VoIP performance after analyzing various scheduling algorithms. The proposal is the technology which applies more priority processing for VoIP than other applications in cell-edge area based on two-tier scheduling algorithm. The simulation result shows the improvement of VoIP performance in the view point of throughput and BLER.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.