• Journal of Dental Anesthesia and Pain Medicine
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• v.22 no.5
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• pp.339-348
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• 2022

Background: To compare the anesthetic efficacy of supplemental buccal infiltration (BI) (1.7 ml) versus intraligamentary (IL) injection containing 0.4 ml of 4% articaine with 1:100.000 epinephrine after an inferior alveolar nerve block (IANB) with 1.7 ml 2% lidocaine in the first and second mandibular molars diagnosed with irreversible pulpitis (IP). Methods: One hundred subjects diagnosed with IP of either the mandibular first (n = 50) or second molars (n = 50) and failed profound anesthesia following an IANB were selected. They randomly received either the IL or BI techniques of anesthesia. Pain scores on a 170 mm Heft-Parker visual analog scale were recorded initially, before, and during supplemental injections. Furthermore, pulse rate was measured before and after each supplemental injection. During the access cavity preparation and initial filing, no or mild pain was assumed to indicate anesthetic success. The chi-square test, Mann-Whitney U test, and independent samples t-test were used for the analyses. Results: The overall success rates were 80% in the IL group and 74% in the BI group, with no significant difference (P = 0.63). In the first molars, there was no significant difference between the two techniques (P = 0.088). In the second molars, IL injection resulted in a significantly higher success rate (P = 0.017) than BI. IL injection was statistically more successful (P = 0.034) in the second molars (92%) than in the first molars (68%). However, BI was significantly more successful (P = 0.047) in the first molars (88%) than in the second molars (64%). The mean pulse rate increase was significantly higher in the IL group than in the BI group (P < 0.001). Conclusions: Both the IL and BI techniques were advantageous when used as supplemental injections. However, more favorable outcomes were observed when the second molars received IL injection and the first molars received BI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.27-33
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• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• Journal of Advanced Navigation Technology
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• v.22 no.3
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• pp.179-188
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• 2018

In developing avionics systems, safety analysis and evaluation specified in SAE ARP4761 (Methods and Guidelines for Civil Aviation System and Equipment Safety Assessment Process) are carried out to prevent air accidents. Safety analysis requires knowledge of the abnormal state of the system, not its normal state, and its interrelationships with other standards. Therefore, a tool that automatically outputs data which proves compliance with safety certification standards is required. In this study,In this study, Schematized the safety analysis procedure of the specification and studied the method of applying the safety analysis CAD tools to individual procedure. As an example study, ARP4761 analysis was performed on the wheel brake system (WBS) of the ARP4761 appendix.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.7A
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• pp.545-551
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• 2012

In this paper, K-band multi-channel receiver was designed and fabricated for low noise amplification and down conversion to L-band. The fabricated multi-channel receiver incorporates GaAs-HEMT LNA(Low noise amplifier) which provides less than a 2 dB noise figure, IR(Image Rejection) Filter for rejection of image frequency, IR(Image rejection) mixer to reject a image frequency and improve an IMD(Intermodulation Distortion) characteristic. Test results of the fabricated multi-channel receiver show less than a 3.8 dB noise figure, conversion gain of more than 27dB, and IP1dB(Input 1dB Gain Compression Point) of -9.5 dB and over.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8B
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• pp.509-520
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• 2007

In this paper, we propose a real-time sensor node platform that guarantees the real-time scheduling of periodic and aperiodic tasks through a multitask-based software decomposition technique. Since existing sensor networking operation systems available in literature are not capable of supporting the real-time scheduling of periodic and aperiodic tasks, the preemption of aperiodic task with high priority can block periodic tasks, and so periodic tasks are likely to miss their deadlines. This paper presents a comprehensive evaluation of how to structure periodic or aperiodic task decomposition in real-time sensor-networking platforms as regard to guaranteeing the deadlines of all the periodic tasks and aiming to providing aperiodic tasks with average good response time. A case study based on real system experiments is conducted to illustrate the application and efficiency of the multitask-based dynamic component execution environment in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. It shows that our periodic and aperiodic task decomposition technique yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.