• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.293-299
• /
• 2004

An active RC 2nd order Butterworth filter suitable for a baseband channel-selection filter of a direct conversion receiver is presented. The linearity of the 2nd order Butterworth filter is analyzed. In order to improve the linearity of the filter, the operational amplifiers should have a high linear gain and low 3rd harmonic, and the filter should be designed to have large feedback factor. This second order Butterworth filter achieves-14dBV in-channel (400kHz, 500kHz) IIP3, +29dBV out-channel (10MHz, 20.2MHz) IIP3 and 15.6 $nV/\sqrt{Hz}$ input-referred noise and dissipates 10.8mW from a 2.7-V supply. The analysis and experimental results are in good agreement

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.675-681
• /
• 2016

A 41dB gain control range $6^{th}$-order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.9A
• /
• pp.1005-1012
• /
• 2004

In this paper, we have analyzed minimum performance required for W-CDMA Handset from standard and Implemented the receiver for W -COMA Handset. We have derived the noise figure and IIP3 of receiver and determined the selectivity about adjacent channel and minimum performance for front-end stage. Before the Implementation, we have verified the performance using AOS simulator In conclusion, we have implemented the receiver for W-COMA Handset using the heterodyne architecture and performed measurement. Therefore, this paper wlll gIVe a guideline for design of the W -COMA Handset.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.2
• /
• pp.53-57
• /
• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.630-634
• /
• 2004

This paper describes the design of a two stage 1V power supply SiGe Low Noise Amplifier operating at 5.25 GHa for 802.lla wireless LAN application. The achieved performance includes a gain of 17 ㏈, noise figure of 2.7㏈, reflection coefficient of 15 ㏈, IIP3 of -5 ㏈m, and 1-㏈ compression point of -14㏈m. The total power consumption of the circuit was 7 mW including 0.5mW for the bias circuit.

• ETRI Journal
• /
• v.32 no.3
• /
• pp.457-459
• /
• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.7 s.98
• /
• pp.681-689
• /
• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.100-105
• /
• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Proceedings of the IEEK Conference
• /
• 2000.11a
• /
• pp.365-368
• /
• 2000

This paper describes image-rejection down conversion mixer for bluetooth application using 0.35u CMOS process. the proposed architecture is composed of LO phase shifter, mixer core, IF buffer, and IF phase shifter. IF phase shifter is designed using polyphase fillet. Simulation results show conversion gain = l0㏈, input 1㏈ compression point = -15.7㏈m. input third-order intercept point(IIP3) = -4.4㏈m, and image-rejection ratio = 37.8㏈, respectively, at 3V supply voltage, and 15.7㎃ current.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.817-820
• /
• 1999

In this paper, we describes RF receiver module for IMT-2000 handset with 5MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier-, RF SAW filter, Down-converter, IF SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8㏈, 3㏈m at 2.14㎓, conversion gain of downconverter is l0㏈, dynamic range of AGC is 80㏈, and phase noise of PLL is -100 ㏈m, at 100KHz. The receiver sensitivity is -110㏈m, adjacent channel selectivity is -48㏈m.