• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.49-53
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• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.221-221
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• 2013

Vertical LED (VLED) has been recognized as a way to obtain the high-power LED due to their advantages [1]. However, approximately 4% of the light generated from the active region is extracted, if the light extraction from side walls and back side is neglected because of Fresnel reflection (FR) and total internal reflection (TIR) [2,3]. In this study, the optical simulation of the VLED with the various microstructures was performed. Among them, the microlens having the diameter of 3 ${\mu}m$ and the height of 1.5 ${\mu}m$ shown the best result was chosen, and then, optimized microlens was formed on a GaN template using conventional semiconductor process. Various microstructures were proposed to improve the light extraction efficiency (LEE) of the VLED for the simulation. The LEE was simulated using LightTools based on a Monte Carlo ray tracing. The microstructures with hemisphere, cone, truncated and cylinder pattern having diameter of 3 ${\mu}m$ were employed on the top layer of the VLED respectively. The improvement of the LEE by using the microstructure is 87% for the hemisphere, 77% for the cone, 53% for the truncated, 21% for the cylinder, compared with the LEE of the flat surface at the reflectance of 85%. The LEE was increased by 88% at the height of 1.5 ${\mu}m$, compared with the LEE of the flat surface. We found that the microlens on the top layer is the most suitable for increasing the LEE. In order to apply the proposed microlens on n-GaN surface, we fabricated microlens on a GaN template. A photoresist array having hexagonal-closed packed microlens was fabricated on the GaN template. Then, optimization of etching the GaN template was performed using a dry etching process with ICP-RIE. The dry etching carried out using a gas mixture of Cl2 and Ar, each having a flow rate of 16 sccm and 10 sccm, respectively with RF power of 50 W, ICP power of 900 W and chamber pressure of 2 mTorr was the optimum etching condition as shown in Fig. 2(a).

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.220-220
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• 2013

Surface-normal transmission electro-absorption modulator (EAM) are attractive for high-definition (HD) three-dimensional (3D) imaging application due to its features such as small system volume and simple epitaxial structure [1,2]. However, EAM in order to be used for HD 3D imaging system requires uniform modulation performance over large area. To achieve highly uniform modulation performance of EAM at the operating wavelength of 850 nm, it is extremely important to remove the GaAs substrate over large area since GaAs material has high absorption coefficient below 870 nm which corresponds to band-edge energy of GaAs (1.424 eV). In this study, we propose and experimentally demonstrate a transmission EAM in which highly selective backside etching methods which include lapping, dry etching and wet etching is carried out to remove the GaAs substrate for achieving highly uniform modulation performance. First, lapping process on GaAs substrate was carried out for different lapping speeds (5 rpm, 7 rpm, 10 rpm) and the thickness was measured over different areas of surface. For a lapping speed of 5 rpm, a highly uniform surface over a large area ($2{\times}1\;mm^2$) was obtained. Second, optimization of inductive coupled plasma-reactive ion etching (ICP-RIE) was carried out to achieve anisotropy and high etch rate. The dry etching carried out using a gas mixture of SiCl4 and Ar, each having a flow rate of 10 sccm and 40 sccm, respectively with an RF power of 50 W, ICP power of 400 W and chamber pressure of 2 mTorr was the optimum etching condition. Last, the rest of GaAs substrate was successfully removed by highly selective backside wet etching with pH adjusted solution of citric acid and hydrogen peroxide. Citric acid/hydrogen peroxide etching solution having a volume ratio of 5:1 was the best etching condition which provides not only high selectivity of 235:1 between GaAs and AlAs but also good etching profile [3]. The fabricated transmission EAM array have an amplitude modulation of more than 50% at the bias voltage of -9 V and maintains high uniformity of >90% over large area ($2{\times}1\;mm^2$). These results show that the fabricated transmission EAM with substrate removed is an excellent candidate to be used as an optical shutter for HD 3D imaging application.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.389-390
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• 2012

In this study, we fabricate a superhydrophobic surface made of hierarchical nanostructures that combine wax crystalline structure with moth-eye structure using vacuum cluster system and measure their hydrophobicity and durability. Since the lotus effect was found, much work has been done on studying self-cleaning surface for decades. The surface of lotus leaf consists of multi-level layers of micro scale papillose epidermal cells and epicuticular wax crystalloids [1]. This hierarchical structure has superhydrophobic property because the sufficiently rough surface allows air pockets to form easily below the liquid, the so-called Cassie state, so that the relatively small area of water/solid interface makes the energetic cost associated with corresponding water/air interfaces smaller than the energy gained [2]. Various nanostructures have been reported for fabricating the self-cleaning surface but in general, they have the problem of low durability. More than two nanostructures on a surface can be integrated together to increase hydrophobicity and durability of the surface as in the lotus leaf [3,5]. As one of the bio-inspired nanostructures, we introduce a hierarchical nanostructure fabricated with a high vacuum cluster system. A hierarchical nanostructure is a combination of moth-eye structure with an average pitch of 300 nm and height of 700 nm, and the wax crystalline structure with an average width and height of 200 nm. The moth-eye structure is fabricated with deep reactive ion etching (DRIE) process. $SiO_2$ layer is initially deposited on a glass substrate using PECVD in the cluster system. Then, Au seed layer is deposited for a few second using DC sputtering process to provide stochastic mask for etching the underlying $SiO_2$ layer with ICP-RIE so that moth-eye structure can be fabricated. Additionally, n-hexatriacontane paraffin wax ($C_{36}H_{74}$) is deposited on the moth-eye structure in a thermal evaporator and self-recrystallized at $40^{\circ}C$ for 4h [4]. All of steps are conducted utilizing vacuum cluster system to minimize the contamination. The water contact angles are measured by tensiometer. The morphology of the surface is characterized using SEM and AFM and the reflectance is measured by spectrophotometer.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.62-62
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• 2003

고밀도 유도결합 플라즈마(high density inductively coupled plasma) 식각은 GaAs 이종접합 양극성 트랜지스터(HBTs)와 고속전자 이동도 트랜지스터(HEMTs)와 같은 GaAs 기반 반도체의 정교한 패턴을 형성하는데 더욱 많이 이용되고 있다 본 연구는 고밀도 플라즈마 소스(source)인 평판형(planar) 고밀도 유도결합 플라즈마 식각장치를 이용하여 $BCl_3$ 와 $BCl_3/Ar$ 가스에 따른 GaAs 식각결과를 비교 분석하였다. 공정변수는 ICP 소스 파워를 0-500W, RIE 척(chuck) 파워를 0-150W, 공정압력을 0-15 mTorr 이었다. 그리고 가스 유량은 20sccm(standard cubic centimeter per minute)으로 고정시킨 상태에서 Ar 첨가 비율에 따른 GaAs의 식각결과를 관찰하였다. 공정 결과는 식각률(etch rate), GaAs 대 PR의 선택도(selectivity), 표면 거칠기(roughness)와 식각후 표면에 남아 있는 잔류 가스등을 분석하였다. 20 $BCl_3$ 플라즈마를 이용한 GaAs 식각률 보다 Ar이 첨가된 (20-x) $BC1_3/x Ar$ 플라즈마의 식각률이 더 우수하다는 것을 알 수 있었다. 식각률 증가는 Ar 가스의 첨가로 인한 GaAs 반도체와 Ar 플라즈마의 충돌로 나타난 결과로 예측된다. $BCl_3$ 와 $BC1_3/Ar$ 플라즈마에 노출된 GaAs 반도체 모두 표면이 평탄하였고 수직 측벽도 또한 우수하였다. 그리고 표면에 잔류하는 성분은 Ga와 As 이외에 $Cl_2$ 계열의 불순물이 거의 발견되지 않아 매우 깨끗함을 확인하였다. 이번 발표에서는 $BCl_3$ 와 $BCl_3/Ar$ 플라즈마를 이용한 GaAs의 건식식각 비교에 대해 상세하게 보고 할 것이다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.818-824
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• 2006

The effects of high-temperature process required to fabricate the SiC devices on the surface morphology and the electrical characteristics were investigated for 4H-SiC Schottky diodes. The 4H-SiC diodes without a graphite cap layer as a protection layer showed catastrophic increase in an excess current at a forward bias and a leakage current at a reverse bias after high-temperature annealing process. Moreover it seemed to deviate from the conventional Schottky characteristics and to operate as an ohmic contact at the low bias regime. However, the 4H-SiC diodes with the graphite cap still exhibited their good electrical characteristics in spite of a slight increase in the leakage current. Therefore, we found that the graphite cap layer serves well as the protection layer of silicon carbide surface during high-temperature annealing. Based on a closer analysis on electric characteristics, a conductive surface transfiguration layer was suspected to form on the surface of diodes without the graphite cap layer during high-temperature annealing. After removing the surface transfiguration layer using ICP-RIE, Schottky diode without the graphite cap layer and having poor electrical characteristics showed a dramatic improvement in its characteristics including the ideality factor[${\eta}$] of 1.23, the schottky barrier height[${\Phi}$] of 1.39 eV, and the leakage current of $7.75\{times}10^{-8}\;A/cm^{2}$ at the reverse bias of -10 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.464-464
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• 2010

A few years ago, for maintaining high stability and production yield of production equipment in a semiconductor fab, on-line monitoring of wafers is required, so that semiconductor manufacturers are investigating a software based process controlling scheme known as virtual metrology (VM). As semiconductor technology develops, the cost of fabrication tool/facility has reached its budget limit, and reducing metrology cost can obviously help to keep semiconductor manufacturing cost. By virtue of prediction, VM enables wafer-level control (or even down to site level), reduces within-lot variability, and increases process capability, $C_{pk}$. In this research, we have practiced VM on $SiO_2$ etch rate with optical emission spectroscopy(OES) data acquired in-situ while the process parameters are simultaneously correlated. To build process model of $SiO_2$ via, we first performed a series of etch runs according to the statistically designed experiment, called design of experiments (DOE). OES data are automatically logged with etch rate, and some OES spectra that correlated with $SiO_2$ etch rate is selected. Once the feature of OES data is selected, the preprocessed OES spectra is then used for in-situ sensor based VM modeling. ICP-RIE using 葰.56MHz, manufactured by Plasmart, Ltd. is employed in this experiment, and single fiber-optic attached for in-situ OES data acquisition. Before applying statistical feature selection, empirical feature selection of OES data is initially performed in order not to fall in a statistical misleading, which causes from random noise or large variation of insignificantly correlated responses with process itself. The accuracy of the proposed VM is still need to be developed in order to successfully replace the existing metrology, but it is no doubt that VM can support engineering decision of "go or not go" in the consecutive processing step.