• Journal of the Microelectronics and Packaging Society
• /
• v.23 no.4
• /
• pp.19-24
• /
• 2016

Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.4
• /
• pp.91-95
• /
• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.177-179
• /
• 2002

A1$_2$ $O_3$기판재료의 $K_{IC}$ 증가를 위한 재료설계를 시도하였다. 먼저 A1$_2$ $O_3$기판을 구성하는 A1$_2$ $O_3$다층구조물에 적절한 다공성 중간층을 삽입하는 샌드위치 구조물을 제조하였다. 제조된 A1$_2$ $O_3$구조물의 미세구조를 관찰하였고, Vickers 경도와 three-point bending test를 통해서 단일조성 구조물과 샌드위치 구조물의 경도와 인성 측정치를 비교하였다. 다공층을 삽입한 A1$_2$ $O_3$샌드위치 구조물의 Single-Edge Notched Beam이 단일 조성의 구조물에 비해 파괴강도와 인성이 향상되는 결과를 얻었다.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.2
• /
• pp.29-33
• /
• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.3
• /
• pp.1-7
• /
• 1999

A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.19-25
• /
• 2008

In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.4
• /
• pp.1-7
• /
• 2018

As the performance and density of IC (integrated circuit) devices increase, power and signal integrities in the global interconnects of advanced packaging technologies are becoming more difficult. Thus, the global interconnect technologies should be designed to accommodate increased input/output (I/O) counts, improved power grid network integrity, reduced RC delay, and improved electrical crosstalk stability. This requirement resulted in the fine-pitch interconnects with a low-k dielectric in 3D packaging or wafer level packaging structure. This paper reviews an organic-inorganic hybrid material as a potential dielectric candidate for the global interconnects. An organic-inorganic hybrid material called polysiloxane can provide spin process without high temperature curing, an excellent dielectric constant, and good mechanical properties.

• Journal of the Microelectronics and Packaging Society
• /
• v.29 no.1
• /
• pp.1-6
• /
• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.4
• /
• pp.9-17
• /
• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of Sensor Science and Technology
• /
• v.27 no.5
• /
• pp.300-305
• /
• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.