• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
• /
• pp.183-184
• /
• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• International Journal of Quality Innovation
• /
• 제6권3호
• /
• pp.70-94
• /
• 2005

The IC packaging industry heavily relies on shop floor information, necessitating the development of a model to flexibly define shop floor information and timely handle manufacturing data. This study presents a novel data model of product manufacturing flow to define shop floor information to effectively respond to accelerated developments in IC package industry. The proposed data model consists of four modules: operation template setup, general process setup, enhanced bill of manufacture (EBOMfr) setup, and work-order process setup. The data model can flexibly define the required shop floor information and decision rules for shop floor product manufacturing flow, allowing one to easily adopt changes of the product and on the shop floor. However, to handle floor dynamics of the IC packaging industry, this work also proposes a WIP (i.e. work-in-process) system for monitoring and controlling the product manufacturing flow on the shop floor. The WIP system integrates the data model with a WIP execution module. Furthermore, an illustrative example, the MIRL WIP System, developed by Mechanical Industrial Research Laboratories of Industrial Technology Research Institute, demonstrates the effectiveness of the proposed model.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제54권7호
• /
• pp.315-318
• /
• 2005

The effect of plasma cleaning was examined on package delamination phenomena in the integrated circuit (IC) packaging process. Without plasma cleaning, delamination was observed for all three experimental treatments applied after the packaging step, which include bake of If, reflow, and bake of If followed by reflow However, no delamination was observed when the plasma cleaning was performed before and after the wire bonding step. Plasma cleaning was found to be a critical step to improve the reliability of the package by reducing the possibility of contact failure between die pad and bonding wire.

• 안전기술
• /
• 제144호
• /
• pp.14-15
• /
• 2009

몸을 움츠리게 하는 차가운 날씨, 아침 일찍부터 두꺼운 외투를 걸치고 길을 나선다. 비가 온 뒤라 초겨울 하늘은 hds통 짙푸른 색으로 구름 한 점 없이 맑다. 충남 천안시 외국인 산업단지내에 위치한 LDI(LCD Drive IC) 제품 Package 전문반도체 회사 스테코, 이곳의 환경안전보건 파트를 책임지고 있는 이상천 안전관리자를 만났다.

• 전자통신동향분석
• /
• 제4권4호
• /
• pp.17-33
• /
• 1989

Hermetic 패키지는 재질 특성상 Plastic 패키지보다 환경내구성이 우수하고 수명이 긴 장점이 있으나, 가격이 높고 사용자의 주문에 의한 수작업으로 수급이 어려운 단점이 있다. 한편 Plastic 패키지는 가격이 낮고 수급이 용이한 반면 환경 특히 습기로 인한 고장으로 Hermetic 패키지보다 신뢰도가 낮아서 고신뢰도를 요구하는 군사용 및 산업용기기에서의 사용은 기피되어 왔다. 그러나 최근 Plastic 패키지의 단점을 개선하려는 노력으로 반도체칩의 수율 향상과 더불어 습기에 강한 재료가 개발되고 웨이퍼 제조기술이 발전됨에 따라 Plastic 패키지의 신뢰도가 향상되어 통신기기등 산업용 기기에까지 사용영역을 확대해 가고 있다. 또한 국내의 통신시장 개방에 따라 통신시스팀의 성능개선 및 신뢰성 제고를 통한 대외 경쟁력이 요구되어 통신시스팀에 Plastic 패키지 사용에 대한 인식이 증대하는 추세이다. 본고에서는 IC 패키지(Hermetic, Plastic)의 특성 및 성능을 비교 분석하고 이와 병행하여 Plastic 패키지의 최근 기술동향을 파악함으로써 통신시스팀에 사용하는 IC 패키지에 대한 고려사항을 제시하였다.

• 한국신뢰성학회지:신뢰성응용연구
• /
• 제16권4호
• /
• pp.347-355
• /
• 2016

Purpose: With the advance of miniaturization of electronic products, stacked packages of high density semiconductors are commonly used. Potential failure modes and mechanisms of stacked packages are identified. Methods: Failure modes and mechanisms of thin chip stacked packages are determined through the categorization and failure analysis: delamination, non-wet, crack, ESD, EMI and the process related damages. Results: Those failure modes are not easy to find and require excessive amount time and effort for analysis and subsequent improvement. Conclusion: In this study, a method of estimating the failure rate based on the strength measurement is suggested.

• 대한전자공학회논문지
• /
• 제25권6호
• /
• pp.637-646
• /
• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• 한국공작기계학회:학술대회논문집
• /
• 한국공작기계학회 1995년도 추계학술대회 논문집
• /
• pp.64-67
• /
• 1995

Transfer Molding is currently the most widely used process for encapsulation integrated circuits(;IC). Although the process has been introduced over 20 years ago, generating billions of parts each year, it is far from being optimized. With each new mold, epoxy mold, epoxy mold compound, and lead-frame, lengthy period and expensive qualification runs have to be performed to minimized defects ranging from wire sweep, incomplete fill, and internal voids etc. This studies describes how simulation can be applied to transfer molding to yield acceptable design and processing parameter. The non-isothermal filling of non-newtonian reactive epoxy molding compound(;EMC) in a multi-cavity mold is analyzed. Sensitivity analysis is conducted to investigate the influence of process deviations on the final molded profile. This study trend is carried out by following some heuristic process guidelines.

• Journal of Welding and Joining
• /
• 제16권4호
• /
• pp.92-97
• /
• 1998

Because of the low melting temperature of solder, each temperature cycle initiates an irrecoverable creep deformation at the solder interconnection which connects the package body with the PCB. The crack starts and propagates from the position where the creep deformation is maximized. This work has tried to compare and analyze the thermal fatigue life of solder interconnection which is affected by the lead material, the size of die pad, chip thickness, and interface delamination of 48-Pin TSOP under the temperature cycle ($0^{\circ}C$~1$25^{\circ}C$). The crack initiation position and thermal fatigue life which are calculated by using FEA method are well matched with the results of experiments. The thermal Fatigue life of copper lead frame is extended around 3.6 times longer than that of alloy 42 lead frame. It is maximized when the chip size is matched with the length of the lead. It tends to be extended as the thickness of chip got thinner. As the interfacial delamination between die pad and EMC is increased, the thermal fatigue life tends to decrease in the beginning of delamination, and increase after the delamination grew after 45% of the length of die pad.

• ETRI Journal
• /
• 제34권5호
• /
• pp.706-712
• /
• 2012

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.