• Journal of Power Electronics
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• 제11권2호
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• pp.188-193
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• 2011

A highly efficient AC-DC converter for small wind power generation systems using a brushless DC generator (BLDCG) is presented in this paper. The market standard AC-DC converter for a BLDCG consists of a three-phase diode rectifier and a boost DC-DC converter, which has an IGBT and a fast recovery diode (FRD). This kind of two-stage solution basically suffers from a large amount of conduction loss and the efficiency greatly decreases under a light load, or at a low current, because of the switching devices with a P-N junction. In order to overcome this low efficiency, especially at a low current, a three-phase bridgcless converter consisting of three upper side FRDs and three lower side Super Junction FETs is presented. In the overall operating speed region, including the cut-in speed, the efficiency of the proposed converter is improved by up to 99%. Such a remarkable result is validated and compared with conventional solutions by calculating the power loss based on I-V curves and the switching loss data of the adopted commercial switches and the current waveforms obtained through PSIM simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.205-208
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

• ETRI Journal
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• 제41권2호
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• pp.254-261
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• 2019

Distinct from conventional energy-harvesting (EH) technologies, such as the use of photovoltaic, piezoelectric, and thermoelectric effects, betavoltaic energy conversion can consistently generate uniform electric power, independent of environmental variations, and provide a constant output of high DC voltage, even under conditions of ultra-low-power EH. It can also dramatically reduce the energy loss incurred in the processes of voltage boosting and regulation. This study realized betavoltaic cells comprised of p-i-n junctions based on silicon carbide, fabricated through a customized semiconductor recipe, and a Ni foil plated with a Ni-63 radioisotope. The betavoltaic energy converter (BEC) includes an array of 16 parallel-connected betavoltaic cells. Experimental results demonstrate that the series and parallel connections of two BECs result in an open-circuit voltage $V_{oc}$ of 3.06 V with a short-circuit current $I_{sc}$ of 48.5 nA, and a $V_{oc}$ of 1.50 V with an $I_{sc}$ of 92.6 nA, respectively. The capacitor charging efficiency in terms of the current generated from the two series-connected BECs was measured to be approximately 90.7%.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.223-226
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• 2003

This paper presents a high-frequency ZVS-PWM boost chopper-fed DC-DC converter with a single active auxiliary edge-resonant snubber which is used for power conditioner such as solar photovoltaic generation and fuel cell generation. The experimental results of boost chopper fed ZVS-PWM DC-DC converter are evaluated. In audition to its switching voltage and current waveforms, and the switching v-i trajectory of the power devices are discussed and compared with the conventional hard switching DC-DC converter treated here. The temperature performance of IGBT module,, efficiency, and EMI noise characteristics of this ZVS-PWM DC-DC converter using IGBTs are measured and evaluated from an experimental point of view.

• 센서학회지
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• 제6권3호
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• pp.194-199
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• 1997

자기센서가 전압이나 전류의 형태 그대로 출력되는 경우에 발생되는 잡음 유입 및 전압 손실 문제를 개선하기 위하여 소자부는 CMOS공정을 이용하여, 포화영역에서 동작하는 2 drain의 MAGFET을 설계 제작하고, 연산증폭기를 이용한 I-V변환회로, VCO(Voltage Controlled Oscillator)를 만들고 Schmitt trigger에 의한 주파수(Pulse) 변환회로의 시스템부를 하이브릿드 IC로 구성하여 packaging했다. 이 때 자기센서 절대감도는 1.9 V/T, 적감도는 $3.2{\times}10^{4}\;V/A{\cdot}T$ 이었으며 190 kHz/T의 안정된 출력 주파수 특성을 얻을 수 있었다.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.1-8
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• 2005

System-on-glass를 위해 poly-Si TFT로 면적이 작으면서도 리플전압을 최소화한 DC-DC 전압 변환회로를 개발하였다. 전압 변환회로는 전하 펌핑 회로, 문턱전압 변화를 보상한 비교기, 오실레이터, 버퍼, 다중 위상 클럭을 만들기 위한 지연 회로로 구성된다. 제안한 다중 위상 클럭킹을 적용함으로써 클럭 주파수 또는 필터링 캐패시터의 증가 없이도 낮은 출력 리플전압을 얻음으로써 DC-DC 변환기의 면적을 최소화 하였다. 제안한 DC-DC 변환회로를 제작하여 측정한 결과 $R_{out}=100k\Omega,\;C_{out}=100pF$, 그리고 $f_{clk}=1MHz$에서 Dickson 구조와 기존의 cross-coupled 구조에서의 리플전압은 각각 590mv와 215mv인 반면 4-위상 클럭킹을 적용한 구조에서는 123mV이다. 그리고 50mV의 리플전압을 가지기 위해 필요한 필터링 캐패시터의 크기는 $I_{out}=100uA$와 $f_{clk}=1MHz$에서 Dickson 구조와 기존의 cross-coupled 구조에서는 각각 1029pF와 575pF인 반면 4-위상과 6-위상 클럭킹을 적용한 구조에서는 단지 290pF와 157pF만이 각각 요구된다. 구조별 효율로는 Dickson 구조의 전하 펌프에서는 $59\%$, 기존의 cross-coupled 구조와 본 논문에서 제안한 4-위상을 적용한 cross-coupled 구조의 전하 펌프에서는 $65.7\%$와 $65.3\%$의 효율을 각각 가진다.

• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.53-57
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• 2002

The solar energy is purity and infinity. Solar power converter were used to convert the electrical energy from the solar arrays to a stable and reliable power source. So many countries research this solar energy system The photovoltaic system is construct many solar cell array. In this paper, new implementation solar system was showed buck converter that V-I curve produced. This system can be used to study the short-term and long-term performances of solar cell and efficiency. This system is a far more cost effective and reliable replacement for field and outdoor flight testing. Study of buck converter, analysis and control series or parallels connection characteristics of solar cell way.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.875-880
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• 2018

This paper proposes a novel combined compensation structure in the infrared receiver chip. For the infrared communication chip, the current-voltage (I-V) convert circuit is crucial and important. The circuit is composed by the transimpedance amplifier (TIA) and the combined compensation structures. The TIA converts the incited photons into photocurrent. In order to amplify the photocurrent and avoid the saturation, the TIA uses the combined compensation circuit. This novel compensation structure has the low frequency compensation and high frequency compensation circuit. The low frequency compensation circuit rejects the low frequency photocurrent in the ambient light preventing the saturation. The high frequency compensation circuit raises the high frequency input impedance preserving the sensitivity to the signal of interest. This circuit was implemented in a $0.6{\mu}m$ BiCMOS process. Simulation of the proposed circuit is carried out in the Cadence software, with the 3V power supply, it achieves a low frequency photocurrent rejection and the gain keeps 109dB ranging from 10nA to $300{\mu}A$. The test result fits the simulation and all the results exploit the validity of the circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.