• Journal of Power Electronics
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• v.19 no.1
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• pp.158-167
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• 2019

This research comparatively studies three kinds of flux regulation methods, namely, stored capacitor discharge pulse (SCDP), constant current source pulse (CCSP), and quantitative flux regulation pulse (QFRP), which are used for hybrid permanent magnet (PM) axial field flux-switching memory machines (HPM-AFFSMMs). Through an analysis of the operation principle and the series hybrid PM flux regulation mechanism of the objective machine, the circuit topologies and flux regulation process of these flux regulation methods are addressed in detail. On the basis of a simulation, the flux regulation characteristics of the researched machine during the magnetization and demagnetization processes are comparatively evaluated. Then, machine performance, including back EMF, direct and quadrature axis inductances, and magnetization and demagnetization characteristics, is quantitatively investigated. Results show that the QFRP enables the HPM-AFFSMM to achieve a less harmonic component of back EMF by approximately 7.28% and 7.97% at the magnetization and demagnetization states, respectively, and a more complete magnetization process than the SCDP and CCSP.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.67-78
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• 2016

The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.

• Earthquakes and Structures
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• v.27 no.1
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• pp.57-67
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• 2024

To assess the seismic performance of Plate-Shell Integrated Concrete Liquid-Storage Structure (PSICLSS), a scaled test model was constructed. This model incorporated a hybrid isolation system, which combined shape memory alloy (SMA), lead-cored rubber isolation bearing (LRB) and sliding isolation bearing (SB). By conducting shaking table test, the dynamic responses of both non-isolated and hybrid-isolated PSICLSS were analyzed. The results show that the hybrid isolation system can effectively reduce the acceleration and displacement responses of the structure. However, it also results in an increase in local hydrodynamic pressure and liquid sloshing height. Under extreme earthquake action, the displacement of isolation layer is small. When vertical ground motion is taken into account, the shock absorption rate of horizontal acceleration decreases. The peak hydrodynamic pressure increases significantly, and the peak hydrodynamic pressure position also changes. The maximum displacement of isolation layer increases, the residual displacement decreases.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• Journal of Computing Science and Engineering
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• v.11 no.2
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• pp.69-77
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• 2017

Recent GPUs have adopted cache memory to benefit general-purpose GPU (GPGPU) programs. However, unlike CPU programs, GPGPU programs typically have considerably less temporal/spatial locality. Moreover, the L1 data cache is used by many threads that access a data size typically considerably larger than the L1 cache, making it critical to bypass L1 data cache intelligently to enhance GPU cache performance. In this paper, we examine GPU cache access behavior and propose a simple hardware-based GPU cache bypassing method that can be applied to GPU applications without recompiling programs. Moreover, we introduce a hybrid method that integrates static profiling information and hardware-based bypassing to further enhance performance. Our experimental results reveal that hardware-based cache bypassing can boost performance for most benchmarks, and the hybrid method can achieve performance comparable to state-of-the-art compiler-based bypassing with considerably less profiling cost.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.209-218
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• 2016

This paper proposes a new lifetime aware buffer mapping method of a synchronous dataflow (SDF) graph on a hybrid memory system with DRAM and PRAM. Since the number of write operations on PRAM is limited, the number of written samples on PRAM is minimized to maximize the lifetime of PRAM. We improve the utilization of DRAM by mapping more buffers on DRAM through buffer sharing. The problem is formulated formally and solved by an optimal approach of an answer set programming. In experiment, the buffer mapping method with buffer sharing improves the PRAM lifetime by 63%.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.48-55
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• 2022

This paper proposes a battery remaining useful life (RUL) prediction method using a deep learning-based EMD-CNN-LSTM hybrid method. The proposed method pre-processes capacity data by applying empirical mode decomposition (EMD) and predicts the remaining useful life using CNN-LSTM. CNN-LSTM is a hybrid method that combines convolution neural network (CNN), which analyzes spatial features, and long short term memory (LSTM), which is a deep learning technique that processes time series data analysis. The performance of the proposed remaining useful life prediction method is verified using the battery aging experiment data provided by the NASA Ames Prognostics Center of Excellence and shows higher accuracy than does the conventional method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.199-203
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• 2017

Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.793-794
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• 2011

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.