• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.369-369
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• 2006

Compatibilizers contribute to many processes in polymer industry, such as manufacturing polymer blends and composites. They are usually designed to be block or graft form which is combined in polar and non-polar parts in the first synthesis process level, for example, the general form of maleic anhydride (MA) as a compatiblizer is a grafted counterpart. However, the process of making the compatibilizer is related to the first synthesis level and it has some problems, such as high cost, poor processability, limitation on use and properties, and so on. So, in order to improve its poor processability and overcome the limitation on use, we developed compatibilizers which have various chemical forms by high intensity ultrasound and super critical fluid nitrogen in polymer melt reactive extrusion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.149-158
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• 1994

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.619-633
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• 1993

A new High level hardware Description Language, ASPHODEL(Algorithm Synthesis Pascal Hardware for Optimal Design and Efficient Language), and its algorithm compiler for high level synthesis are described in this paper. The new HDL, appropriated to the description of algorithmic level and lower, models VLSI circuits as an abstracted block which is consisted of input/output ports and hierachical processors to control VLSI complexities with efficiency. Also, in order to improve the descriptive power, popular Pascal programming language is modified to build ASPHODEL syntax rules. ASPHODEL algorithm compiler generates an intermediate form through lexical and syntax analysis from ASPHODEL source codes. To show the validation of presented language and its compiler, those are applied to practical design examples.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.53-67
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• 1994

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.1
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• pp.33-49
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• 1995

Simulated annealing(SA) has been admitted as a general purpose optimization technique which can be utilized for almost all kinds of combinatorial optimization problems without much difficulty. But there are still some weak points to be resolved, one of which is the slow speed of convergence. In this study, we carefully review various previous efforts to improve SA and propose some variations of SA which can enhance the speed of convergence to the optimum solution. Then, we apply the revised SA algorithms to the scheduling and hardware allocation problems occurring in high-level synthesis(HLS) of VLSI design. We confirm the efficiency of the proposed methods through several HLS examples.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.410-413
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• 2000

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.64-73
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• 1992

This paper presents the design of multi-level logic optimization algorithm and the development of the SMILE system based on the algorithm. Considering the fanin constraints in algorithmic level, SMILE performs global and local optimization in a predefined sequence using heuristic information. Designed under the Sogang Silicon Compiler design environment, SMILE takes the SLIF netlist or Berkeley equation formats obtained from high-level synthesis process, and generates the optimized circuits in the same format. Experimental results show that SMILE produces the promising results for some circuits from MCNC benchmarks, comparable to the popularly used multi-level logic optimization system, MIS.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.1
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• pp.39-44
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• 2005

Scheduling for digital system synthesis is assigning each operation in a control/data flow graph(CDFG) to a specific control step without violating precedence relation. It is one of the most important tasks due to its direct influence on the performance of the hardware synthesized. In this paper, we propose a resource-constrained scheduling algorithm. Our algorithm first analyzes the given CDFG to determine the number of functional units of each type, then assigns each operation to a control step while satisfying the constraints. It also tries to improve the solution iteratively by adjusting the number of functional units using the results collected from the previous scheduling. Experiments were performed to test the performance of the proposed algorithm, and results are presented