• Macromolecular Research
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• 제14권2호
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• pp.140-145
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• 2006

E-science refers to the large-scale science that will increasingly be carried out through distributed global collaborations enabled by the Internet. The Grid is a service-oriented architecture proposed to provide access to very large data collections, very large scale computing resources and remote facilities. Web services, which are server applications, enable online access to service providers. Web portal interfaces can further hide the complexity of accessing facility's services. The main use of synchrotron radiation (SR) facilities by protein crystallographers is to collect the best possible diffraction data for reasonably well defined problems. Significant effort is therefore being made throughout the world to automate SR protein crystallography facilities so scientists can achieve high throughput, even if they are not expert in all the techniques. By applying the above technologies, the e-HTPX project, a distributed computing infrastructure, was designed to help scientists remotely plan, initiate and monitor experiments for protein crystallographic structure determination. A description of both the hardware and control software is given together in this paper.

• 대한전자공학회논문지TC
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• 제47권10호
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• pp.27-35
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• 2010

무선 패킷 망에서 무선 자원과 무선 단말의 전력을 얼마나 효율적으로 사용할 수 있는가 하는 것은 무선 패킷 망 보급을 위한 기본 해결 과제이다. 이에 단말의 전력 소모를 줄이면서 무선 망 용량 (capacity)을 증가시키는 기법으로 전송 파워 조절 기법이 주목받고 있다. 무선 패킷 망에 전송 파워 조절 기법을 적용할 때 전송 파워의 세기에 따라 공평한 전송성능을 보장하지 못하고 기아상태에 이르는 전송 불공평성 문제가 지금까지 깊이 연구되지 않고 있다. 이에 본 연구에서는 전송 파워의 세기에 따른 성능 불공평성을 경쟁자 수의 차이에 의한 불공평한 매체 접근 기회에 있음을 분석을 통해 보이고 불공평성을 해결하기 위한 간단한 물리-맥 (PHY-MAC) 계층 간 접근법을 제안한다.

• International Journal of Computer Science & Network Security
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• 제22권9호
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• 인터넷정보학회논문지
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• 제8권1호
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• pp.15-23
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• 2007

무선 랜(IEEE 802,11)은 신뢰적인 데이터 전송을 위해 기존 TCP를 사용하고 무선 신호의 단절, 간섭, 감쇠 영향으로 인하여 혼잡하지 않은 상태에서 의도하지 않은 패킷손실을 유발한다. 무선 랜에서의 TCP는 패킷손실을 혼잡으로 판단하고, 혼잡제어 알고리즘을 작동하므로 전반적인 전송률이 감소된다. 본 논문은 무선 랜에서의 전송률 증가를 위해 유선 네트워크 고속전송 기법인 TCP 버퍼튜닝을 적용하여 TCP 버퍼크기와 전송률과의 상관관계를 분석한다. 분석을 통해 버퍼크기 증가에 관계없이 더 이상의 전송률이 증가되지 않는 특정 버퍼 한계점을 찾고, 이를 우리는 최대버퍼한계(Maximum Buffer Threshold, MBT)라 정의한다. 최대버퍼한계를 산출하기 위해 실제 연주를 통해 음악파일을 생성한 후 이를 이용하여 실험을 한다. 최대 버퍼한계 기반 TCP 버퍼튜닝은 운영체제 기본 버퍼크기에서의 무선 전송률과 비교하여 송수신간 RTT가 5ms 구간에서 20.3%, RTT 10ms에서 21.4%, RTT 20ms에서 45.4% 전송률이 향상된다. 또한 특정 RTT 구간에서 최대 전송률을 97%의 정확도로 예측하고, 최대버퍼한계 이상으로 TCP 버퍼크기를 설정하는 것은 전송률 증가에 영향이 없음을 확인한다.

• 한국컴퓨터정보학회논문지
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• 제13권5호
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• pp.45-52
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• 2008

본 논문에서는 고성능 컴퓨팅 시스템의 성능 향상을 위한 효율적인 동적 작업부하 균등화 정책을 제안한다. 이 정책은 시스템 자원인 CPU와 메모리를 효율적으로 사용하여 고성능 컴퓨팅 시스템의 처리량을 최대화하고, 각 작업의 수행시간을 최소화한다. 또한 이 정책은 수행중인 작업의 메모리 요구량과 각 노드의 부하 상태를 파악하여 작업을 동적으로 할당한다. 이때 작업을 할당받은 노드가 과부하 상태가 되면 다른 노드로 작업을 이주시켜 각 노드의 작업부하를 균등하게 유지함으로써 작업의 대기시간을 줄이고, 각 작업의 수행시간을 단축한다. 본 논문에서는 시뮬레이션을 통하여 제안하는 동적 작업부하 균등화 정책이 기존의 메모리 기반의 작업부하 균등화 정책에 비해 고성능 컴퓨팅 시스템의 성능 향상 면에서 우수함을 보인다.

• 한국컴퓨터정보학회논문지
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• 제22권4호
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• pp.17-24
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• 2017

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• 전자통신동향분석
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• 제35권4호
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• 한국컴퓨터정보학회논문지
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• 제21권1호
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• pp.147-153
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• 2016

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• 한국컴퓨터정보학회논문지
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• 제21권1호
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• pp.125-129
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• 2016

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Journal of Information Processing Systems
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• 제18권1호
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.