• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• Journal of Convergence for Information Technology
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• v.8 no.6
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• pp.237-242
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• 2018

There are various 'wireless communication technologies' around us. Wireless mobile communication has evolved through various stages, and its utilization is also diverse. However, due to the development of wireless communication technology, the demand for frequency resources is much higher than the supply, so frequency shortage is serious. Recently, 'visible light communication' has been attracting attention as an emerging communication technology that can solve the frequency shortage. 'Visible light communication' is a communication method based on serial data transmission / reception, and there is a difficulty in transmitting / receiving parallel data because the transmitter and the receiver are arbitrarily present. In this paper, we have studied parallel data processing of visible light communication. We could solve the problem by analyzing parallel data using image processing. Through this study, communication performance can be verified through I / O data comparison by implementing parallel data analysis method. It is expected that diversity in parallel data analysis will be presented through the results.