• Title/Summary/Keyword: High reactive substrate

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High Speed Cu Filling Into TSV by Pulsed Current for 3 Dimensional Chip Stacking (3차원 실장용 TSV의 펄스전류 파형을 이용한 고속 Cu도금 충전)

  • Kim, In Rak;Park, Jun Kyu;Chu, Yong Cheol;Jung, Jae Pil
    • Korean Journal of Metals and Materials
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    • v.48 no.7
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    • pp.667-673
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    • 2010
  • Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

Fabrication and characterization of $WSi_2$ nanocrystals memory device with $SiO_2$ / $HfO_2$ / $Al_2O_3$ tunnel layer

  • Lee, Hyo-Jun;Lee, Dong-Uk;Kim, Eun-Kyu;Son, Jung-Woo;Cho, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.134-134
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    • 2011
  • High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

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Preparation of the SiO2 Films with Low-Dit by Low Temperature Oxidation Process (저온 산화공정에 의해 낮은 Dit를 갖는 실리콘 산화막의 제조)

  • Jeon, Bup-Ju;Jung, Il-Hyun
    • Applied Chemistry for Engineering
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    • v.9 no.7
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    • pp.990-997
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    • 1998
  • In this work, the $SiO_2$ films on the silicon substrate with different orientations were first prepared by the low temperature process using the ECR plasma diffusion as a function of microwave power and oxidation time. Before and after thermal treatment, the surface morphology, Si/O ratio from physicochemical properties, and the electrical properties of the oxide films were also investigated. The oxidation rate increased with microwave power, while surface morphology showed the nonuniform due to etching. The film quality, therefore, was lowered with increasing the defect by etching and the content of positive oxide ions in the oxide films from bulk by higher self-DC bias. The content of positive oxide ions in the oxide films with different Si orientations showed Si(100) < Si(111) < poly Si. The defects in $Si/SiO_2$ interface of $SiO_2$ film could be decreased by annealing, while $Q_{it}$ and $Q_f$ were independent of thermal treatment and the dependent on concentration of reactive oxide ions and self-DC bias of substrate. At microwave power of 300, and 400 W, the high quality $SiO_2$ film that had lower surface roughness and defect in $Si/SiO_2$ interface was obtained. The value of interface trap density, then, was ${\sim}9{\times}10^{10}cm^{-2}eV^{-1}$.

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Processing and Biological Activity of Gelatin Hydrolysate from Branchiostegus japonicus Scales (옥돔(Branchiostegus japonicus) 비늘 유래 젤라틴의 가수분해 및 가수분해물의 기능성)

  • Ahn, Yong-Seok;Lee, Won-Woo;Lee, Seung-Hong;Ahn, Gin-Nae;Ko, Chang-Ik;Oh, Chang-Kyung;Oh, Myung-Cheol;Kim, Dong-Woo;Jeon, You-Jin;Kim, Soo-Hyun
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.42 no.5
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    • pp.417-425
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    • 2009
  • The potential utility of fish scales to the functional food industry has been investigated due to its antioxidant and antihypertensive characteristics. In this study, we report on the reactive oxygen species (ROS) scavenging and angiotensin I converting enzyme (ACE) inhibitory activities of gelatin hydrolysates processed from Branchiostegus japonicus scales, which are also high in protein content (about 46.1%). We prepared the enzymatic gelatin hydrolysates with four proteases (${\alpha}$-chymotrypsin, Alcalase, Neutrase and trypsin) from B. japonicus scale gelatin, which was prepared according to different reaction times, substrate/enzyme ratios and substrate concentrations. The enzymatic hydrolytic degrees of the gelatin increased time-dependently up to 6 hrs, while the Alcalase gelatin hydrolysates showed the highest hydrolysis degrees compared to the others. Furthermore, gelatin hydrolysates of Neutrase and ${\alpha}$-chymotrypsin showed the highest DPPH radical and $H_2O_2$ scavenging activities ($IC_{50}$ value; 9.18 mg/mL and 9.74 mg/mL), respectively. However, the activities were not significant (P<0.05). We also observed that the four gelatin hydrolysates significantly increased ACE inhibitory activities from approximately 20% to 60% (P<0.05), Among them, the Alcalase gelatin hydrolysates showed the higher ACE inhibitory activity ($IC_{50}$ value; 0.73 mg/mL) compared to the others. These results suggest that the enzymatic gelatin hydrolysates prepared from B. japonicus scales may possess a potentially useful function as an ACE inhibitory agent. As such, the utility of B. japonicus scales should be given due consideration for application in the functional food industry.

Metalorganic Chemical Vapor Deposition of Copper Films on TiN Substrates Using Direct Liquid Injection of (hfac)Cu(vtmos) Precursor ((hfac)Cu(vtmos)의 액체분사법에 의한 TiN 기판상 구리박막의 유기금속 화학증착 특성)

  • Jun, Chi-Hoon;Kim, Youn-Tae;Kim, Dai-Ryong
    • Korean Journal of Materials Research
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    • v.9 no.12
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    • pp.1196-1204
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    • 1999
  • We have carried out copper MOCVD(metalorganic chemical vapor deposition) onto the reactive sputtered PVD-TiN and rapid thermal converted RTP-TiN substrates using direct liquid injection for effective delivery of the (hfac)Cu(vtmos) [$C_{10}H_{13}O_{5}CuF_{6}$Si: 1,1,1,5,5,5-hexafluoro-2,4- pentadionato (vinyltrimethoxysilane) copper (I)] precursor. Especially, the influences of deposition conditions and the substrate type on growth rate, crystal structure, microstructure, and electrical resistivity of copper deposits have been discussed. It is found that the film growth with 0.2ccm precursor flow rate become mass-transfer controlled up to Ar flow rate of 200sccm and pick-up rate controlled at a vaporizer above 1.0Torr reactor pressure. The surface-reaction controlled region from 155 to 225$^{\circ}C$ at 0.6Torr reactor pressure results in the apparent activation energies of 12.7~14.1kcal/mol, and above 224$^{\circ}C$ the growth rate with $H_2$ addition could be improved compared to the pure Ar carrier. The Cu/RTP-TiN structures which have high copper nucleation density in initial stage of growth show more pronounced (111) preferred orientations and lower electrical resistivities than those on PVD-TiN. The variation of electrical resistivity with substrate temperature reflects the three types of film microstructure changes, showing the lowest value for the deposit at 165$^{\circ}C$ with small grains of good contacts.

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Mechanical Properties of HfN/Si$_3$N$_4$and NbN/$Si_3N_4$Multilayer Coatings (HfN/Si$_3$N$_4$와 NbN/$Si_3N_4$다층박막의 기계적 특성)

  • Jeong, Jin-Jung;Hwang, Seon-Geun;Lee, Jong-Mu
    • Korean Journal of Materials Research
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    • v.11 no.3
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    • pp.236-242
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    • 2001
  • HfN/Si$_3$N$_4$and NbN/Si$_3$N$_4$ multilayer coatings were deposited onto a high speed tool steel substrate by reactive sputtering and their mechanical properties were evaluated in terms of the dependence of hardness and adhesion strength on the sputter deposition process parameters. The hardnesses of both HfN/Si$_3$N$_4$and NbN/Si$_3$N$_4$ multiplayer coatings increase up to the flux ratio of 0.4 but nearly do not change after that as the $N_2$/Ar flux ratio in nitride sputter deposition increases. The hardnesses of both multiplayer coatings nearly do not change with annealing at low temperatures but decrease owing to oxidation with annealing at a high temperature like 80$0^{\circ}C$ after depositing the layers by sputtering. Post-annealing at low temperatures increases the adhesion strength of the multilayers. but high temperature annealing is not desirable since it decreases the adhesion strength besides the hardness deterioration.

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Formation of Passivation Layer and Its Effect on the Defect Generation during Trench Etching (트렌티 식각시 식각 방지막의 형성과 이들이 결함 생성에 미치는 영향)

  • Lee, Ju-Wook;Kim, Sang-Gi;Kim, Jong-Dae;Koo, Jin-Gon;Lee, Jeong-Yong;Nam, Kee-Soo
    • Korean Journal of Materials Research
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    • v.8 no.7
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    • pp.634-640
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    • 1998
  • A well- shaped trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy. The trench was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $0_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching, resulted in the well filled trench with oxide and polysilicon by subsequent deposition. The passivation layer of lateral etching was mainly composed of $SiO_xF_y$ $SiO_xBr_y$ confirmed by chemical analysis. It also affects the generation and distribution of lattice defects. Most of etch induced defects were found in the edge region of the trench bottom within the depth of 10$\AA$. They are generally decreased with the thickness of residue layer and almost disappeared below the uni¬formly thick residue layer. While the formation of crystalline defects in silicon substrate mainly depends on the incident angle and energy of etch species, the region of surface defects on the thickness of residue layer formed during trench etching.

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Fabrication of MEMS Test Socket for BGA IC Packages (MEMS 공정을 이용한 BGA IC 패키지용 테스트 소켓의 제작)

  • Kim, Sang-Won;Cho, Chan-Seob;Nam, Jae-Woo;Kim, Bong-Hwan;Lee, Jong-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.1-5
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    • 2010
  • We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

Ginsenoside Rb1 and compound K improve insulin signaling and inhibit ER stress-associated NLRP3 inflammasome activation in adipose tissue

  • Chen, Weijie;Wang, Junlian;Luo, Yong;Wang, Tao;Li, Xiaochun;Li, Aiyun;Li, Jia;Liu, Kang;Liu, Baolin
    • Journal of Ginseng Research
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    • v.40 no.4
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    • pp.351-358
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    • 2016
  • Background: This study was designed to investigate whether ginsenoside Rb1 (Rb1) and compound K (CK) ameliorated insulin resistance by suppressing endoplasmic reticulum (ER) stress-induced inflammation in adipose tissue. Methods: To induce ER stress, epididymal adipose tissue from mice or differentiated 3T3 adipocytes were exposed to high glucose. The effects of Rb1 and CK on reactive oxygen species production, ER stress, TXNIP/NLRP3 inflammasome activation, inflammation, insulin signaling activation, and glucose uptake were detected by western blot, emzyme-linked immunosorbent assay, or fluorometry. Results: Rb1 and CK suppressed ER stress by dephosphorylation of $IRE1{\alpha}$ and PERK, thereby reducing TXNIP-associated NLRP3 inflammasome activation in adipose tissue. As a result, Rb1 and CK inhibited IL-$1{\beta}$ maturation and downstream inflammatory factor IL-6 secretion. Inflammatory molecules induced insulin resistance by upregulating phosphorylation of insulin receptor substrate-1 at serine residues and impairing insulin PI3K/Akt signaling, leading to decreased glucose uptake by adipocytes. Rb1 and CK reversed these changes by inhibiting ER stress-induced inflammation and ameliorating insulin resistance, thereby improving the insulin IRS-1/PI3K/Akt-signaling pathway in adipose tissue. Conclusion: Rb1 and CK inhibited inflammation and improved insulin signaling in adipose tissue by suppressing ER stress-associated NLRP3 inflammation activation. These findings offered novel insight into the mechanism by which Rb1 and CK ameliorate insulin resistance in adipose tissue.

Formation of $TiN/TiSi_2$-bilayer by PVD method (PVD 방법에 의한 $TiN/TiSi_2$-bilayer 형성)

  • Choe, Chi-Gyu;Gang, Min-Seong;Kim, Deok-Su;Lee, Gwang-Man;Hwang, Chan-Yong;Seo, Gyeong-Su;Lee, Jeong-Yong;Kim, Geon-Ho
    • Korean Journal of Materials Research
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    • v.8 no.12
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    • pp.1182-1189
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    • 1998
  • High quality $TiN/TiSi_2$-bilayers were formed on the Si(100) substrate at room temperature and at $600^{\circ}C$ first by coevaporation of stoichiometric Si and Ti(Si:Ti = 2:1) fellowed by Ti reactive deposition in N, gas ambient, and in situ annealing in ultrahigh vacuum. Stoichiometric $Ti_{0.}N_{0.5}$, films with (111) texture and $C54-TiSi_2$ films were grown by annealing at temperatures above $700^{\circ}C$. $TiN/C54-TiSi_2$/Si(100) interface was clear and flat without agglomoration, and $CS4-TiSi_2$ film was epitxailly grown. The sheet resistance of the $TiN/TiSi_2$- bilayer decreased as the annealing temperature increased and about $2.5\omega/\textrm{cm}^2$ was obtained from the sample annealed over $700^{\circ}C$.

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