• Journal of Pharmaceutical Investigation
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• v.30 no.3
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• pp.191-199
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• 2000

Genomics is providing targets faster than we can validate them and combinatorial chemistry is providing new chemical entities faster than we can screen them. Historically, the drug discovery cascade has been established as a sequential process initiated with a potency screening against a selected biological target. In this sequential process, pharmacokinetics was often regarded as a low-throughput activity. Typically, limited pharmacokinetics studies would be conducted prior to acceptance of a compound for safety evaluation and, as a result, compounds often failed to reach a clinical testing due to unfavorable pharmacokinetic characteristics. A new paradigm in drug discovery has emerged in which the entire sample collection is rapidly screened using robotized high-throughput assays at the outset of the program. Higher-throughput pharmacokinetics (HTPK) is being achieved through introduction of new techniques, including automation for sample preparation and new experimental approaches. A number of in vitro and in vivo methods are being developed for the HTPK. In vitro studies, in which many cell lines are used to screen absorption and metabolism, are generally faster than in vivo screening, and, in this sense, in vitro screening is often considered as a real HTPK. Despite the elegance of the in vitro models, however, in vivo screenings are always essential for the final confirmation. Among these in vivo methods, cassette dosing technique, is believed the methods that is applicable in the screening of pharmacokinetics of many compounds at a time. The widespread use of liquid chromatography (LC) interfaced to mass spectrometry (MS) or tandem mass spectrometry (MS/MS) allowed the feasibility of the cassette dosing technique. Another approach to increase the throughput of in vivo screening of pharmacokinetics is to reduce the number of sample analysis. Two common approaches are used for this purpose. First, samples from identical study designs but that contain different drug candidate can be pooled to produce single set of samples, thus, reducing sample to be analyzed. Second, for a single test compound, serial plasma samples can be pooled to produce a single composite sample for analysis. In this review, we validated the issue whether the second method can be applied to practical screening of in vivo pharmacokinetics using data from seven of our previous bioequivalence studies. For a given drug, equally spaced serial plasma samples were pooled to achieve a 'Pooled Concentration' for the drug. An area under the plasma drug concentration-time curve (AUC) was then calculated theoretically using the pooled concentration and the predicted AUC value was statistically compared with the traditionally calculated AUC value. The comparison revealed that the sample pooling method generated reasonably accurate AUC values when compared with those obtained by the traditional approach. It is especially noteworthy that the accuracy was obtained by the analysis of only one sample instead of analyses of a number of samples that necessitates a significant man-power and time. Thus, we propose the sample pooling method as an alternative to in vivo pharmacokinetic approach in the selection potential lead(s) from combinatorial libraries.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.10a
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• pp.305-310
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• 2004

The Hot Embossing Lithography(HEL) as a method for the fabrication of nanostructure with polymer is becoming increasingly important because of its simple process, low cost, high replication fidelity and relatively high throughput. In this study, we investigated the characteristics of hot embossing lithography as a nanoreplication technique. To grasp characteristics of nano patterning rheology by process parameters(embossing temperature, pressure and time), we have carried out various experiments by using the DVD(400nm pattern width) and Blu-ray nickel stamps(150nm pattern width). During the hot embossing process, we have observed the characteristics of the size effect. The quality of products made by hot embossing is affected by its cooling shrinkage. The demolding process at the glass transition temperature results in low quality because of the shrinkage of the polymer. Therefore, the quantification of the temperature condition is essential for the replication of high quality.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2006.05a
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• pp.86-90
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• 2006

Nanoimprint lithography (NIL) is a novel method to fabricate nanometer scale patterns. It is a simple process with low cost, high throughput and high resolution. NIL process creates patterns by the mechanical deformation of imprint resist and physical contact process. This physical contact process causes the stiction between the resist and the stamp. Stiction becomes a key issue especially in the stamps including narrow pattern size and wide area during NIL process development. The antistiction layer coating using fluorocarbon is very effective to prevent this problem and ensure successful NIL. In this paper, the concept of antistiction coating is explained and different preparation methods for nanoimprinting are briefly discussed.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.1
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• pp.25-49
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• 1997

Printed circuit board (PCB) assembly line configuration is characterized by very long set-up times and high work in process (WIP) inventory level. The scheduling method can significantly reduce the set-up times and WIP inventory level. Greedy sequence dependent scheduling (GSDS) method is proposed based on the current methods. The proposed method is compared with the current method in terms of three performance measures: line throughput, average WIP inventory level, and implementation complexity.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.12 no.19
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• pp.79-88
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• 1989

This characteristics of process industries are high capital intensity, relatively long and sequence dependent setup times, and extremely limited capacity resources. The lot sizing, sequencing and limited capacity resources factors must he considered for production scheduling in these industries. This paper presents a mixed integer programming model for production scheduling. The economic trade offs between capacitated lot sizing flow shop scheduling and sequence dependent setup times also be compared with SMITH-DANIELS's model. As a results, it is shown that this paper has lower total cost, more efficient throughput than SMITH-DANIELS's model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.175-184
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• 2001

In this study, the improved throughput and stability in device fabrication could be obtained by applying CMP process to STi structue in 0.18 um semiconductor device. To employ the CMP process in STI structure, the Reverse Moat Process used to be added after STI Fill, as a result, the process became more complex and the defect were seriously increased than they had been,. Removal rate of each thin film in STI CMP was not uniform, so, the device must have been affected. That is, in case of excessive CMP, the damage on the active area was occurred, and in the case of insufficient CMP nitride remaining was happened on that area. Both of them deteriorated device characteristics. As a solution to these problems, the development of slurry having high removal rate and high oxide to nitride selectivity has been studied. The process using this slurry afford low defect levels, improved yield, and a simplified process flow. In this study, we evaluated the 'High Selectivity Slurry' to do a global planarization without reverse moat step, and also we evaluated EPD(Eend Point Detection) system with which 'in-situ end point detection' is possible.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.