• Journal of Sensor Science and Technology
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• v.7 no.5
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• pp.350-355
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• 1998

We fabricated a photoconductive cell made of polycrystalline CdS thick film which has high photo-sensitivity using a print/sintering method. The resultant grain size is about $4\;{\mu}m$. When $CuCl_2$ of 0.06 to 0.12 mg is added, the sensitivity and the ratio of photocurrent to dark current are 0.8 and $10^5$, respectively. The response wavelength is 511 nm. The rise and decay response times are 50 and 20 ms, respectively. In addition, the maximum power dissipation is beyond 80mW. We noticed that the addition of $CuCl_2$ between 0.06 and 0.12 mg to 1g of CdS results in a reliable formation of photoconductive sensor.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.19-23
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• 2014

For the application of light-emitting diodes (LEDs) for general illumination, the development of high power LEDs chips became more essential. For these reasons, recently, modified vertical LEDs have been developed to meet various requirements such as better heat dissipation, higher light extraction and less cost of production. In this research, we investigate the effect of Size and Array of N-GaN contact on operation voltage with new structured padless vertical LED. We changed the size and array of N-electrodes and investigated how they affect the operation voltage of LEDs. We simulated the current crowding and expected operation voltage for different N-contact structures with commercial LED simulator. Also, we fabricated the padless vertical LED chips and measured the electrical property. From the simulation, we could know that the larger size and denser array of n-electrodes could make operation voltage decrease. These results are well in accordance with those measured values of real padless vertical LED chips.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• Advances in aircraft and spacecraft science
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• v.2 no.2
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• pp.169-182
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• 2015

Aeronautics engine cooling is one of the biggest problems that engineers have tried to solve since the beginning of human flight. Systems like radiators should solve this purpose and they have been studied extensively and various solutions have been found to aid the heat dissipation in the engine zone. Special interest has been given to air coolers in order to guide the air flow on engine and lower the high temperatures achieved by the engine in flow conditions. The aircraft companies need faster and faster tools to design their solutions so the development of tools that allow to quickly assess the effectiveness of an cooling system is appreciated. This paper tries to develop a methodology capable of providing such support to companies by means of some application examples. In this work the development of a new methodology for the analysis and the design of oil cooling systems for aerospace applications is presented. The aim is to speed up the simulation of the oil cooling devices in different operative conditions in order to establish the effectiveness and the critical aspects of these devices. Steady turbulent flow simulations are carried out considering the air as ideal-gas with a constant-averaged specific heat. The heat exchanger is simulated using porous media models. The numerical model is first tested on Piaggio P180 considering the pressure losses and temperature increases within the heat exchanger in the several operative data available for this device. In particular, thermal power transferred to cooling air is assumed equal to that nominal of real heat exchanger and the pressure losses are reproduced setting the viscous and internal resistance coefficients of the porous media numerical model. To account for turbulence, the k-${\omega}$ SST model is considered with Low- Re correction enabled. Some applications are then shown for this methodology while final results are shown in terms of pressure, temperature contours and streamlines.

• Journal of Sensor Science and Technology
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• v.1 no.1
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• pp.53-57
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• 1992

We report the crystal growth and the electro-optic characteristics of $CdS_{1-x}Se_{x}$ thin films. $CdS_{1-x}Se_{x}$ thin films wire deposited on the alumina plate by electron beam evaporation technique in pressure of $1.5{\times}10^{-7}$ torr, voltage of 4kV, current of 2.5mA and substrate temperature of $300^{\circ}C$. The deposited $CdS_{1-x}Se_{x}$ thin films were proved to be a polycrystal with hexagonal structure through X-ray diffraction patterns. $CdS_{1-x}Se_{x}$ photoconductive films showed high photoconductivity after annealing at $550^{\circ}C$ for 30 minutes. And the films have been investigated the Hall effect, photocurrent spectra, sensitivity, maximum allowable power dissipation and response time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.57-64
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• 2005

This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology.

• Journal of Sensor Science and Technology
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• v.5 no.6
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• pp.25-34
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• 1996

In this paper, we have designed signal conditioning circuitry for piezoresistive pressure sensor. Signal conditioning circuitry consists of voltage reference circuit for sensor driving voltage and instrument amplifier for sensor signal amplification. Signal conditioning circuitry is simulated using HSPICE in a single poly double metal $1.5\;{\mu}m$ BiCMOS technology. Simulation results of band-gap reference circuit showed that temperature coefficient of $21\;ppm/^{\circ}C$ at the temperature range of $0\;{\sim}\;70^{\circ}C$ and PSRR of 80 dB. Simulation results of BiCMOS amplifier showed that dc voltage gain, offset voltage, CMRR, CMR and PSRR are outperformed to CMOS and Bipolar, but power dissipation and noise voltage were more improved in CMOS than BiCMOS and Bipolar. Designed signal conditioning circuitry showed high input impedance, low offset and good CMRR, therefore, it is possible to apply sensor and instrument signal conditioning circuitry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.