• Proceedings of the Korean Vacuum Society Conference
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• 1996.02a
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• pp.175-175
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• 1996

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.453-456
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• 2017

이 논문에서는 HEMT 소자에서 사용되는 3-5족 물질의 1차원 구조에 대하여 self-consistent Schrodinger Poisson solver를 수치해석적으로 구현하였다. 이를 바탕으로 갈륨과 인듐의 비율이 줄고 알루미늄의 조성비가 증가하는 상황에 대하여 시뮬레이션 해본 결과 알루미늄의 조성비가 더 큰 것이 그렇지 않은 것보다 이차원 전자가스 채널에 더 많은 전자를 모이게 하는 것을 관찰할 수 있었다.

• Electronics and Telecommunications Trends
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• v.3 no.1
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• pp.86-98
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• 1988

III-V 화합물 반도체에서 불순물에 의한 다층박막조직의 조성 혼합현상과 quantum well heterostructure laser 제조에의 응용기술을 소개하였으며, 지금까지의 조성 혼합기구로 제안된 모델의 타당성에 대해 상세히 논의하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.05a
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• pp.128-129
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• 1994

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.84-87
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• 2002

The Si$_{1-x}$ Gex/Si surface alloy (x = 0.3, 0.4 and 0.5), which are prepared by solid source MBE and have the SiGe epilayer thickness of 50$\AA$, are annealed with different parameters. The surface structure analyses of the heterostructure samples are made on a triple-axis X-ray diffractometer in grazing incidence X-ray diffraction (GIXRD) geometry. It has been found that with different annealing time (1.5h, 18h, 64h) and annealing temperature (550 $^{\circ}C$, 750 $^{\circ}C$), the SiGe epilayer experienced different strain relaxation process, which was deduced from the GIXRD measurements of the in-plane (220) diffraction peak of Si(001) substrate and the relevant (220) surface diffraction of SiGe epilayer. The results show that the stress relieving and the lateral strain relaxation in the SiGe/Si heterostructure can be promoted by correct annealing, which is very helpful for the preparation of SiGe/Si strained superlattice with fine strain crystallization..

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.682-687
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• 2014

We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage ($V_{th}$) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the $V_{th}$ and the on-current were decreased. The on-current reduction was caused by the positive shift of the $V_{th}$ and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.370-373
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• 2003

Superluminescent diodes(SLDs) are the optimum light sources for application in optical measurement systems such as fiber gyroscopes, optical time domain reflectometers, and to short and medium distance optical communication systems. The broadband characteristics of SLDs reduce Rayleigh backscattering noise, polarization noise, and the bias offset due to the nonlinear Kerr effect in fiber gyro systems. In this paper, in order to suppress lasing oscillation, we introduced a laterally tilted SCH(Separate Confinement Heterostructure)-SLD with a window region. An output power of 11mW has been achieved at 200mA injection current at 25$^{\circ}C$. At 120mA, parallel and perpendicular to the junction were 31$^{\circ}$${\times}$38$^{\circ}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1135-1142
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• 2000

In this study, we fabricated a 1.55um polarization-insensitive semiconductor optical amplifier(SOA) with rectangular buried heterostructure using a InGaAsP/InP double heterostructure wafer. Measured characteristics of the fabricated SOA are that 3dR bandwidth is 35nm and 3dB saturation output power is 4dBm. Maximum gain under the 150mA CW driving condition is 19.4dB. We measured the ASE(amplified spontanouse emission) Power spectrum or n and TM mode in the fabricated SOA using ASE measurement system and knew that distributions of the TE and TM mode about the maxinum region are nearly coincident. this shows the fabricated SOA is a polarization-insensitive.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.194-195
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• 2006

개인 휴대 통신 기기의 급속한 발달로 인해 부품의 소형화, 고집적화가 중요한 요소로 대두되고 있으며 이를 위해서는 모듈내부에 3차원적인 수동소자의 내장이 가능한 LTCC (Low Temperature Co-fired Ceramics) 공정이 각광받고 있다. Embedded Capacitor를 제조하기 위해 유전율이 7.6과 6.5인 LTCC 재료를 이종접합 하여 제조하였으며 이종재료의 수축거동 차이에 의한 camber가 발생하였다. 이를 해결하고 또한 고주파 부품용 정밀회로 패턴을 구 현하기 위해 PLAS 방식의 Constrained Sintering 공정을 적용하여 camber 문제를 해결하였으며 capacitance 값이 두 이종재료의 유전율과 1:1로 비례하지 않았는데 이는 유전율 65 tape에 잔존하는 기공 때문으로 판단되며 미세구조로써 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.1-6
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• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.