• Title/Summary/Keyword: Harmonics level

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Power Noise Suppression Methods Using Bead with Spiral Resonator (비드와 나선형 공진기를 이용한 전원 노이즈 저감 방안 연구)

  • Chung, Tong-Ho;Kang, Hee-Do;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.2
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    • pp.152-160
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    • 2013
  • In this paper, to the aim of wideband SSN(Simultaneous Switching Noise) suppression characteristic, investigation of spiral resonator are used in conjunction with bead which is commonly used for noise suppression method. Bead works effectively to suppress the power noise up to the first harmonic of fundamental frequency, 0.8 GHz, and spiral resonator suppress noise well in the frequency range of SRF(Self Resonance Frequency) which is inversely proportional to the length of spiral. Thus, when bead used in conjunction with a spiral the noise suppression characteristic is determined by the one of higher impedance element of the two in the frequency range and achieves more broadband filtering characteristic. The case for using 22 nH bead turns out 4.8, 2.0, 0, and, 0.6 dB, and the case for using 22 nH bead in conjunction with 3-turns spiral achieves more wideband characteristic of 9.5, 8.3, 6.1, and 9.9 dB power noise suppression performances at the first, second, third, and fourth harmonics, respectively. The peak-to-peak voltage levels decrease from 76 mV to 56 mV using 22 nH bead, and the level decrease rapidly to 34 mV when using in conjunction with bead and 3-turn spiral. Thus more wideband SSN suppression characteristic can be achieved using bead with spiral.

A Study on the Utility Interactive Photovoltaic System Using a Chopper and PWM Voltage Source Inverter for Air Conditioner a Clinic room (병실 냉.난방을 위한 초퍼와 PWM 전압형 인버터를 이용한 계통 연계형 태양광 발전시스템에 관한 연구)

  • Hwang, L.H.;Na, S.K.
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.2
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    • pp.360-369
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    • 2008
  • The solar cells should be operated at the maximum power point because its output characteristics were greatly fluctuated on the variation of insolation, temperature and load. It is necessary to install an inverter among electric power converts by means of the output power of solar cell is DC. The inverter is operated supply a sinusoidal current and voltage to the load and the interactive utility line. In this paper, the proposes a photovoltaic system is designed with a step up chopper and single phase PWM voltage source inverter. Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper is operated in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature for solar cell has typical dropping character. The single phase PWM voltage source inverter is consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be develop continuously by connecting with the source of electric power for ordinary using. It can be cause the efect of saving electric power, from 10 to 20%. The single phase PWM voltage source inverter operates in situation, that its output voltage is in same phase with the utility voltage. The inverter are supplies an ac power with high factor and low level of harmonics to the load and the utility power system.

Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process (pHEMT 공정을 이용한 저손실, 고전력 4중 대역용 SP6T 스위치 칩의 설계 및 제작)

  • Kwon, Tae-Min;Park, Yong-Min;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.584-597
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    • 2011
  • In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.