• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.90-92
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• 2005

In this paper, we design a digital protection IED(Intelligent Electric Device) for a distributed power system in connection with power grid. The device can measure various elements for protection and communicate with another devices through network. The protection IED is composed of specific function modules: signal process module which converts analog signal from PT and CT handle algorithm to digital one; communication module for connection with another IEDs; input/output module for user-interfaces; main control module for control the whole modules. A general purpose DSP board with TMS320C2812 is used in the IED. Experiments with the power system simulator DOBLE have been made to verily the proposed hardware system.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.9
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• pp.816-824
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• 2004

In this paper, the framework for accelerating the development of personal robots is presented, which includes the technology such as modularization with its own processing and standardization open to the other developers. Its basic elements are Module-D(Module of DRP I) characterized functionally and VM-D(Virtual Machine of DRP I) arbitrating Module-Ds. They can suggest the effective ways for integrating various robotic components and interfacing among them. Based on this framework, we developed a fully modularized personal robot called DRP I(Dynamically Reconfigurable Personal robot). Its hardware components are easily attached to and detached from the whole system. In addition, each software of the components is functionally distributed. For the materialization of the proposed idea, we mainly focus on the dynamically reconfigurable feature of DRP I.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.837-840
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• 1999

In this paper, we design and verify the hardware circuit that performs PLCP(Physical Layer Convergence Protocol) protocol functions of physical layer in IEEE 802.11 frequency hopping WLAN(Wireless Local Area Network). Altera MAX＋PLUS I $I^{〔1〕}$ is used as a design tool. The designed circuit consists of control register module to interface with upper layer, FIFO module to transmit/receive data with upper layer, TX function module, and RX function module. It is verified that the developed circuit conforms well to the IEEE 802.11 standard specification and can support both 1Mbps and 2 Mbps transmission rate by simulation. The developed circuits can be utilized for the implementation of protocol processor in wireless LAN areas.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.325-333
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• 2007

A PV system inverter test module using RTDS was developed and performance test of a commercial PV inverter was carried out. The developed module consists of one RTDS hardware rack, RTDS software models representing PV array and simple distribution system, and two power amplifiers that was specifically designed for generating power corresponding to signals from RTDS. Performance test results verified effectiveness and reliability of the test module. It is expected that the developed test module may help PV inverter manufacturers improve ana test their systems in the developing stage.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.10
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• pp.2501-2513
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• 1994

In this paper, a compact, light-weight, universal, spherical 3-degree-of-freedom, parallel-structured manual controller with high reflecting-force capability is implemented. First, the position analysis, kinematic modeling and analysis, force reflecting transformation, and applied force control schemes for a parallel structured 3 degree-of-freedom spherical system have been described. Then, a brief description of the system integration, its actual implementation hardware, and its preliminary analysis results are presented. The implemented parallel 3 degree-of-freedom spherical module is equipped with high gear-ratio reducers, and the friction due to the reducers is minimized by employing a force control algorithm, which results in a "power steering" effect for enhanced smoothness and transparency (for compactness and reduced weight).d weight).

• Journal of the Korean Society of Industry Convergence
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• v.11 no.3
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• pp.135-140
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• 2008

This paper researched about Development Cutting Tool User Defined Module Based(PMCUDMS) on Simulation that was able to adapt themselves to rapid development of software and hardware to adopt. It is basic research that develops a scheme whereby technic make property. This paper theorized about to realize Cutting Tool User Defined Module Based on Simulation which is developing CNC Software flows from building Windows XP operating system's image that is possible realtime acting and multitasking to correct. And Cutting Tool User Defined Module Based on Simulation component which was consisted of basis OS, NC Code parser, Servo Motor Control, Simulator, Man-Machine Interface.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1257-1263
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• 2008

Recent advances in embedded system technology have brought more dependence on automating train control. While much efforts have been reported to improve electronic hardware's safety, not so much systematic approaches to evaluate software's safety, especially for the vital software running on board train controllers. In this paper, we have developed a software testing tool to evaluate train control system software safety, expecially "Metric Analysis" module. We have reviewed requirements in the international standards and surveyed available tools in the market. From this, we identified the S/W metric analysis module is required for software evaluation. So we have developed S/W metric analysis module for railway signaling systems.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.2
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• pp.15-21
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• 2010

The user authentication using fingerprint information not only provides the convenience but also high security. However, the fingerprint information for user authentication can cause serious problems when it has been compromised. It cannot change like passwords, because the user only has ten fingers on two hands. Recently, there is an increasing research of the fuzzy fingerprint vault system to protect fingerprint information. The research on the problem of fingerprint alignment using geometric hashing technique carried out. This paper proposes the hardware architecture fuzzy fingerprint vault system based on geometric hashing. The proposed architecture consists of software and hardware module. The hardware module has charge of matching between enrollment hash table and verification hash table. Based on the experimental results, the execution time of the proposed system with 36 real minutiae is 0.2 second when 100 chaff minutiae, 0.53 second when 400 chaff minutiae.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.