• Journal of Korea Multimedia Society
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• v.16 no.1
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• pp.100-107
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• 2013

As the eBook market grows fast recently, various eBook viewer solutions such as hardware viewers and software readers came out to the market. We can, however, hardly find mobile eBook interfaces for the reading disabled people who have difficulties in reading for their visual impairment or learning disabilities, or dyslexia. An eBook viewer interfaces for the reading disabled people should be carefully and distinctively designed because the reading disabled people cannot use normal versions of eBook viewer. In this paper, we suggest a eBook viewer interface model to make the reading disabled people read eBooks easily. Depending on the type of the reading disabled people: the full blind, the almost blind, the just learning disabled, our model provides an adaptive interface to make them read eBooks effectively. In addition, unlike the existing simple audio books, we also support annotation systems to make the reading disabled people interact with eBook viewer. To show the effectiveness of our model, we implemented an eBook viewer prototype on an android-based mobile device. We are sure that our model and implementation can make the reading disabled people, who is 10% of all the domestic people, read eBooks effectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1845-1852
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• 2008

The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

• Korean Journal of Comparative Education
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• v.27 no.3
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• pp.101-127
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• 2017

The purpose of this study is to analyze how the debates on learning and learning outcomes in global education agendas have changed and to understand the discourses and issues about learning under the agendas, and finally based on the understanding, to know what is the implication we should take in international education development cooperation in Korea. To do this, this study critically analyzed 1) what is the main features and directions, and 2) the method and limitation in handling learning concept on three major global education forums which are Jomtien global education forum in 1990, Dakar in 2000, and Incheon in 2015. Major finding shows that there are little learning concept discussed in Jomtien and Dakar forums and in SDGs education agenda, learning is vaguely defined and discussed and there are problems of too much focus on learning outcomes itself and absence of study on proper assessment system. Major lessons and implications for international education development cooperation could be stated that postcolonial perspectives and learner centered approaches is required in developing countries's education ecology. And continuous support for sustainable development for learners' capacity should be underlined. We needs to focus on developing software not hardware from the first of educational ODA. Finally, it is needed to embed within pedagogical approaches.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.12
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• pp.645-652
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• 2018

Recently, as South Korea has joined the OSJD, the rules of the OSJD need to be applied to South Korea. Therefore, the railways are connected to the continent railway in terms of software, but the railway systems in neighboring countries have been developed and operated for a long time, and are quite different with some restrictions in terms of hardware. Therefore, this study analyzed the current railway systems of neighboring countries' based on the TSI used in Europe for technical interoperability. A real operation with the operation models within the specific route was assumed and vector functions for the Infrastructure vector & Rolling stock vector were produced. The IOP value was calculated by working out the interfacing matrix value between the infrastructure vector and rolling stock vector. As a result of calculating the IOP in a specific route, which is from Busan South Korea to Vladivostok with the diesel locomotive hauling freight cars, the value was only 22%, which is fairly low in terms of the interoperability. In other words, there are 77.8% restricting items preventing their interoperability. Such restricted causes should be improved to increase the technical interoperability in the long term. Moreover, and when railway systems are constructed and manufactured, it is important to keep IOP 100% to increase the operating efficiency in continental railways.

• The Journal of Industrial Distribution & Business
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• v.12 no.6
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• pp.57-74
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• 2021

Purpose: Before COVID-19 pandemic, Chinese mid/low-priced hotel industry has been steadily growing in recent years, and internal and external competition has been intensifying. Under these circumstances, this study started with a strategic objective to increase the quality of service, thus enabling customer satisfaction and revisit intention. For enhancing the competitiveness of Chinese mid/low-priced hotel business, we plan to establish a model using SERVQUAL, O2O platform, and identify their relationship through empirical analyses. Research design, data and methodology: Through the consideration of the existing literature, this study intended to identify the characteristics of service quality in Chinese mid/low-priced hotels and to consider their impact on customer satisfaction and revisit intention. We also wanted to examine the moderating effect of the O2O platform between the characteristics of service quality and customer satisfaction. A survey was carried out on customers using mid/low-priced hotels in China and empirical analyses were conducted using regression analyses. Results: First, in the hypothesis of service qualities' effects on customer satisfaction were identified with significant positive effects. Second, in the hypothesis of service qualities' effects on revisit intention, "tangibles, reliability, and empathy" have shown significant positive. Third, in the verification of the moderating effect of the O2O platform, there were "positive partial moderating effects" between service qualities and customer satisfaction. Finally, the effect of customer satisfaction on revisit intention was positive significant. Conclusions: In order to satisfy their customers, improvements in service quality should be made first. In addition, customer satisfaction had a positive impact on revisit intention. In order to revitalize Chinese mid/low-priced hotels, differentiation strategy is also needed for specialized customers such as college students, and basically, efforts should be made to optimize the O2O platform. O2O platforms should establish optimal platform construction strategies based on the customer's perspective. After all, in the case of Chinese mid/low-priced hotels, it is necessary to strengthen the construction of the latest hardware infrastructure and O2O platform of software infrastructure, and to improve customers' advanced online and offline experiences. Finally, regarding the hypothesis that was rejected among service qualities' characteristics, we tried to discuss the reason and find the implications of these.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.318-331
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• 2022

With the recent development of hardware computing devices and software based frameworks, machine tasks using deep learning networks are expected to be utilized in various industrial fields and personal IoT devices. However, in order to overcome the limitations of high cost device for utilizing the deep learning network and that the user may not receive the results requested when only the machine task results are transmitted from the server, Collaborative Intelligence (CI) proposed the transmission of feature maps as a solution. In this paper, an efficient compression method for feature maps with vast data sizes to support the CI paradigm was analyzed and presented through experiments. This method increases redundancy by applying feature map reordering to improve compression efficiency in traditional video codecs, and proposes a feature map method that improves compression efficiency and maintains the performance of machine tasks by simultaneously utilizing image compression format and video compression format. As a result of the experiment, the proposed method shows 14.29% gain in BD-rate of BPP and mAP compared to the feature compression anchor of MPEG-VCM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.