• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1125-1132
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• 2023

The importance of networks is gradually expanding in the battlefield environment. As time goes by, the types of tactical data links used in the Korean JTDLS are increasing, and the military's weapon systems equipped with tactical data link systems are increasing. Thorough quality verification is required to provide stable software to the wider battlefield. This study examines how to prepare an environment in which various simulation tests to verify the stability of the Korean JTDLS project can be conducted as diverse as possible using minimal physical space and Hardware resources. Through this, it is possible to improve the completeness of the project and secure the stability of the program, and it is intended to contribute to securing higher stability and reliability by securing maximum test capabilities in a limited test environment even in Linux based system project of a similar environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of Korea Multimedia Society
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• v.13 no.11
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• pp.1715-1727
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• 2010

Although a hand haptic interaction which provides direct and natural sensation is the most natural way of interacting with VR environment, the hand haptic interaction has still limitations with respect to the complexity of articulated hand and related hardware capabilities. Particularly, virtual assembly simulation which refers to the verification process of digital mockup in product development lifecycle is one of the most challenging topics in virtual reality applications. However, hand haptic interaction is considered as a big obstacle, because difficulty initial grasping and non-dextrous manipulation remain as unsolved problems. In this paper, we propose that common hand haptic interactions involves two separate stages with different aspects. We present the hand haptic interaction method enables us to stably grasp a virtual object at initial grasping and delicately manipulate an object at task operating by one's intention. Therefore, proposed method provides the robustness using grasping quality and dextrous manipulation using physically simulation. We conducted experiments to evaluate the effectiveness of our proposed method under different display environments -monoscopic and stereoscopic. From 2-way ANOVA test, we show that the proposed method satisfies two aspects of hand haptic interaction. Finally, we demonstrated an actual application of various assembly simulation for relatively complex models.

• International Journal of Contents
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• v.11 no.1
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• pp.41-51
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• 2015

Management systems for electronic library have been developed on the basis of Client/Server or ASP framework in domestic market for a long time. Therefore, both service provider and user suffer from their high cost and effort in management, maintenance, and repairing of software as well as hardware. Recently in addition, mobile devices like smartphone and tablet PC are frequently used as terminal devices to access computers through the Internet or other networks, sophisticatedly customized or personalized interface for n-screen service became more important issue these days. In this paper, we propose a new scheme of integrated management system for electronic library based on SaaS and Web Standard. We design and implement the proposed scheme applying Electronic Cabinet Guidelines for Web Standard and Universal Code System. Hosted application management style and software on demand style service models based on SaaS are basically applied to develop the management system. Moreover, a newly improved concept of duplication check algorithm in a hierarchical evaluation process is presented and a personalized interface based on web standard is applied to implement the system. Algorithms of duplication check for journal, volume/number, and paper are hierarchically presented with their logic flows. Total framework of our development obeys the standard feature of Electronic Cabinet Guidelines offered by Korea government so that we can accomplish standard of application software, quality improvement of total software, and reusability extension. Scope of our development includes core services of library automation system such as acquisition, list-up, loan-and-return, and their related services. We focus on interoperation compatibility between elementary sub-systems throughout complex network and structural features. Reanalyzing and standardizing each part of the system under the concept on the cloud of service, we construct an integrated development environment for generating, test, operation, and maintenance. Finally, performance analyses are performed about resource usability of server, memory amount used, and response time of server etc. As a result of measurements fulfilled over 5 times at different test points and using different data, the average response time is about 62.9 seconds for 100 clients, which takes about 0.629 seconds per client on the average. We can expect this result makes it possible to operate the system in real-time level proof. Resource usability and memory occupation are also good and moderate comparing to the conventional systems. As total verification tests, we present a simple proof to obey Electronic Cabinet Guidelines and a record of TTA authentication test for topics about SaaS maturity, performance, and application program features.

• Geophysics and Geophysical Exploration
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• v.23 no.3
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• pp.208-214
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• 2020

In this study, we have developed a drone magnetic exploration system (proto-type) using a fluxgate magnetic sensor. Hardware of the system consists of a fluxgate magnetometer, an inertial measurement unit (IMU), a GPS, and a communication module. And we have developed monitoring software, which enables it to transmit the measured data to the ground control system (GCS) in real time. The measured magnetic data are finally saved as 1 Hz data after passing through a notch filter and a band-pass filter. For verification of this system, a preliminary test was conducted to check the magnetic responses of a magnetic object first, then the field test was carried out in two iron mines. We tested the developed system on the field test in Pocheon, Gyeonggi and Jeongseon, Gangwon. The magnetic data from the developed drone system was very similar to those from unmanned airship system developed by Korea Institute of Geoscience and Mineral Resources (KIGAM). As a result, preliminary experiment and field test have demonstrated that this system is applicable for outdoor aeromagnetic exploration. It requires more studies to improve filter function and instrument performance to minimize noise in the future.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.1
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• pp.41-49
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• 2008

Many machineries and equipments are being changing to various and complicated by development of recent technology and arrival of convergence age in distant future. These various and complicate equipments need more precise outcomes and low-power consumption sensors to get close and exact results. In this paper, we proposed fault tolerance and feedback theorem for sensor network and MEMS circuit which has a benefit of energy efficiency through wireless sensor network. The system is provided with independent sensor communication if possible as unused action, using idle condition of system and is proposed the least number of circuits. These technologies compared system efficiency after examining product of each Moving Distance by developed sensor which gives effects to execution of system witch is reduced things like control of management side and requirement for hardware, time, and interaction problems. This system is designed for practical application; however, it can be applied to a normal life and production environment such as "Ubiquitous City", "Factory Automata ion Process", and "Real-time Operating System", etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.55-62
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• 2007

This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.

• Journal of Broadcast Engineering
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• v.25 no.1
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• pp.25-35
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• 2020

Recently, the development of image processing technology, as well as hardware performance, has been continuing the research on 3D point processing technology that provides users with free viewing angle and stereoscopic effect in various fields. Point cloud technology, which is a type of representation of 3D point, has attracted attention in various fields because it can acquired/expressed point precisely. However, since Hundreds of thousands, millions of point are required to represent one 3D point cloud content, there is a disadvantage that a larger amount of storage space is required than a conventional 2D content. For this reason, the MPEG (Moving Picture Experts Group), an international standardization organization, is continuing to research how to efficiently compress, store, and transmit 3D point cloud content to users. In this paper, a V-PCC bitstream generated by a V-PCC (Video-based Point Cloud Compression) encoder proposed by the MPEG-I (Immersive) group is composed of an MPU (Media Processing Unit) defined by the MMT. In addition, by extending the signaling message defined in the MMT standard, a parameter for a segmented transmission method of the 3D point cloud content by area and quality parameters considering the characteristic of the 3D point cloud content, so that the quality parameters can be selectively determined according to the user's request. Finally, in this paper, we verify the result through design/implementation of the verification platform based on the proposed technology.

• Journal of the Korea Society of Computer and Information
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• v.26 no.12
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• pp.151-158
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• 2021

Internet of Things (IoT) technology, which provides services by connecting various objects in the real world and objects in the virtual world based on the Internet, is emerging as a technology that enables a hyper-connected society in the era of the 4th industrial revolution. Since IoT technology is a convergence technology that encompasses devices, networks, platforms, and services, various studies are being conducted. Among these studies, studies on measures that can measure service quality provided by IoT software are still insufficient. IoT software has hardware parts of the Internet of Things, technologies based on them, features of embedded software, and network features. These features are used as elements defining IoT software quality measurement metrics. However, these features are considered in the metrics related to IoT software quality measurement so far. Therefore, this paper presents a metric for reusability measurement among various quality factors of IoT software in consideration of these factors. In particular, since IoT software is used through IoT devices, services in IoT software must be designed to be changed, replaced, or expanded, and metrics that can measure this are very necessary. In this paper, we propose three metrics: changeability, replaceability, and scalability that can measure and evaluate the reusability of IoT software services were presented, and the metrics presented through case studies were verified. It is expected that the service quality verification of IoT software will be carried out through the metrics presented in this paper, thereby contributing to the improvement of users' service satisfaction.