• Nuclear Engineering and Technology
• /
• v.53 no.10
• /
• pp.3327-3334
• /
• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.2661-2663
• /
• 2005

To construct the stable back-up system between mini-hubs, we propose the plan of site diversity of asynchronous mini-hub by monitoring outlink carriers and error data. In this paper, we made hardware and software to control mini-hub system for site diversity back-up by switching SDBS equipment through communication between master mini-hub and slave mini-hub.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.5
• /
• pp.310-318
• /
• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.6 no.9
• /
• pp.2388-2404
• /
• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.895-900
• /
• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• Smart Media Journal
• /
• v.5 no.4
• /
• pp.49-56
• /
• 2016

Various sensor devices has been developed as the wireless Internet and IoT technology are widely used. Recently, open source hardware has evolved for providing various services in IoT environments. However, in comparison to the development of the open source hardware, the development of human resources is missing. In order to solve such a phenomenon, in this paper, we propose a software framework for the embedded software development in open source hardware. The proposed framework provides a fast and intuitive development environment by using the visual programming language and providing fast feedbacks to developers. In addition, we discuss the strengths and weaknesses of the proposed scheme based on the implement on a real board.

• ETRI Journal
• /
• v.29 no.4
• /
• pp.530-532
• /
• 2007

This paper presents a simple method to implement a complete on-line portable wireless holter including an electrocardiogram (ECG) monitoring, processing, and communication protocol. The proposed algorithm significantly reduces the hardware resources of threshold estimation for ECG compression, using the standard deviation updated with each new input signal sample. The new method achieves superior performance in terms of hardware complexity, channel occupation and memory requirements, while keeping the ECG quality at a clinically acceptable level.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.6
• /
• pp.813-818
• /
• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.

• Proceedings of the IEEK Conference
• /
• 2000.06c
• /
• pp.169-172
• /
• 2000

IP Switching is a new routing technology proposed to improve the performance of IP routers. Flow classification is one of the key issues in IP Switching. To achieve better performance, flow classification should be matched to the varying IP traffic and an IP switch should make use of its hardware switching resources as fully as possible. This paper proposes an adaptive flow classification algorithm for IP Switching. By dynamically adjusting the values of its control parameters in response to the present usage of the hardware switching resources, this adaptive algorithm can efficiently match the varying IP traffic and thus improve the performance of an IP switch.

• Proceedings of the Korea Water Resources Association Conference
• /
• 1989.07a
• /
• pp.89-94
• /
• 1989

본 연구는 하천 수질의 종합관리를 위한 sotware 시스템과 hardware 시스템을 개발하는 것이다. Software 시스템은 하천의 오염실태 조사분석 자료를 활용하여 예측모형의 반응식과 제 계수를 도출하고, 수질변동 및 예측모형의 중요지표 수질인자들에 대한 시각적 화면 display 를 위한 그래픽 모듈과 우리나라 오염심화 하천에 알맞는 종합수질 관리용 컴퓨터 프로그램을 개발하므로서 궁극적으로 하천의 한정된 수자원의 최적 활용을 위한 정량적, 정성적 종합수질 관리 시스템을 개발하는 것이다. 또한, Hardware 시스템은 지표 수질인자들을 자동 측정하여 on line, real time 으로 운영 될수 있는 computer supported monitoring network system 과 수질관리를 위한 지역적 수질정보를 위한 network system 을 연구하므로서 control computer system 및 programmable process controllers system 을 구축하고자 한다.