• Journal of IKEEE
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• v.22 no.4
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• pp.1036-1043
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• 2018

This paper presented future power system protection technologies through the HW/SW integration platform with IEC 61850 and IEEE c37.238 standards. To determine the implementation performance of the integrated platform, an example of EVM (Evaluation Module) was constructed to satisfy the standards. The platform has been identified as a future power system integrated IED(Intelligent Electronic Device) HW/SW technology that meets the level of error required by the time sync standard and the level of delay required by protecting the power system.

• Journal of IKEEE
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• v.24 no.1
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• pp.178-185
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• 2020

This paper proposes precise time synchronization-based synchronized sampling structure applied HW/SW platform for LAN-based protection of future digital substations. The integrated software of the proposed platform includes IEC 61850 protocol, IEEE 1588 precision time protocol and synchronized sampling structure. The proposed platform expected to provide a basis of an application of future distributed sensing data-based protection and control methods by providing synchronized measurement among IEDs. The implementation of the proposed HW/SW platform technique was performed using TMDXIDK572 multi-core/multi-processor evaluation module and its time synchronization performance and synchronized sampling function were confirmed through the performance tests.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.878-881
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• 2014

정보시스템은 메인프레임(Mainframe)에서 클라이언트/서버시스템(C/S System), 인터넷 및 인트라넷 시스템을 지나 최근에는 클라우드 컴퓨팅환경으로 발전하고 있다. 이러한 복잡성과 컴퓨팅 환경의 다변함에 따라 시스템 성능 및 용량 산정에 관한 중요성은 점점 부각되고 있다. 이는 기존의 H/W(하드웨어규모산정지침 등)의 방식이 체계적이지 못하고, 다양한 컴퓨팅 환경의 특징을 반영하지 못하기 때문이며 이는 하드웨어 구축비용의 증가 혹은 감소로 실제 요구되는 정보시스템 자원이 과다 또는 과소 산정되는 경우가 발생할 수 있다. 특히 클라우드 컴퓨팅은 막대한 서버자원이 필요하기 때문에 보다 체계적이고 정확하게 HW를 산정하는 것은 사업성공 중요한 요소라 할 수 있다. 클라우드 컴퓨팅의 하드웨어의 용량 산정을 위해서는 우선 IT자원의 성격에 따른 3가지 서비스모델(서비스형소프트웨어, 플랫폼형서비스, 인프라형서비스)에 적합한 용량산정모델을 제시해야 한다. IaaS는 사용자에게 인프라기반의 서비스를 제공하며, PaaS의 경우에는 플랫폼과 OS 등의 개발환경을 제공의 목적이 있기 때문에 HW용량산정을 위해서는 다양한 측면에서의 접근이 요구된다. SaaS는 WEB/WAS의 서비스와 유사한 형태의 서비스 특징을 가지고 있기 때문에 기존 서비스 특징과 클라우드 특징을 도출하기에 적합하다 할 수 있다. 본 연구에서는 SaaS기반의 하드웨어 용량산정에 대한 방법과 기준을 제시하였다. 본 연구결과는 클라우드 컴퓨팅 환경구축 시 HW용량산정에 대한 가이드라인으로 활용 가능하다.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.661-673
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• 2000

In this paper, we propose a Web-based HW/SW Codesign Environment with Distributed Architecture (WebCEDA), then design and implement SpecCharts Specification Environment(ScSE) for specifying systems in WebCEDA. WebCEDA has 3-tier client/server architecture than can remedy disadvantages of existing codesign tools, such as platform dependency, difficulty of extension, absence of collaboraton environment. ScSE includes web interface, SpecCharts editor, HW/SW codesin application sever and SpecCharts translator. To verify the operation of ScSE, we specify several example system using SpecCharts editor, then translate it to VHDL using SpecCharts translator and simulate the translated VHDL codes on synopsys. As the results, we know that ScSE has correct operations, also obtain the following advantages, the reduction in system complexity and the natural abstract design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.449-454
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• 2009

In this paper, we analyze the hardware and software platform for constructing the USN in the vessel environment. Specifically, we analyze the mote technology based on the CC2420 in the hardware platform and analyze the TinyOS platform in the software platform. We also analyze the physical layer of IEEE802.15.4 which is the standard of the USN communication. In the simulation, we evaluate the performance in the physical layer of ZigBee/IEEE 802.15.4 by using the MATLAB and verify the validity of constructing the USN in the vessel environment based on the simulation results.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.476-489
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• 1999

HW/SW codesign is integrated design of systems implemented using both hardware and software components. Many design tools has been developed to support this new paradigm, so far. Current codesign tools are not widely used as been expected because of variety problems - rapidly evolving technology, platform dependency, absence of standard specification method, inconsistent user interface, varying target system, different functionality In this paper, we propose a web-based distributed HW/SW codesign environment to remedy this kinds of problem. Our codesign environment has object-based 3 tier client/server architecture. It supports collaborative workspace through session service. Fully object-oriented design of user interface(OOUI) enables easy extension without change of user Interface. Furthermore it contains transaction server and security server for efficient and safe transfer of design data. To show a validity of our design, we developed prototype of web-based HW/SW codesign environment called WebCEDA. Our model of HW/SW codesign can be used for web-based generic CAD tools.

• Electronics and Telecommunications Trends
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• v.31 no.4
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• pp.65-76
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• 2016

특정 제조사의 단말 또는 운영체제에 의존성이 없는 플랫폼 독립적인 웹은 높은 이식성, 소프트웨어의 재활용, 개발 생산성, 풍부한 개발자 존재, 유지 보수 면에서 장점을 가지나, 화려한 UI/UX를 제공하는 네이티브 응용에 비해 낮은 성능으로 웹 기반의 응용 개발 및 보급이 크게 활성화되지 못했다. 한편 데스크톱은 물론 모바일 단말의 멀티코어 기반 Graphic Processing Unit(GPU), CPU 탑재 등 HW 고사양화와 웹 응용에서도 HW 가속 기능을 활용할 수 있는 표준 제공으로 성능 제약을 극복할 수 있게 되었다. 본고에서는 GPU 발전동향을 살펴보고, 고속 렌더링 및 병렬 연산처리를 요구하는 웹 응용이 GPU기반 HW 가속 기능을 활용할 수 있는 크로노스 그룹의 그래픽 가속(Web Graphics Library: WebGL) 및 컴퓨팅(Web Computing Language: WebCL) 지원 표준 규격을 정리한다. 또한, 최근 차세대 GPU Application Programming Interface(API)로 발표된 Vulkan에 대해 알아보고, 웹 고속화 기술에 적용 가능성에 대해 전망한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.593-605
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• 2014

In this paper, we propose the efficient HW/SW co-design method of light-weight cryptography such as HIGHT, PRESENT and PRINTcipher using GEZEL. At first the symmetric cryptographic algorithms were designed using the GEZEL language which is efficiently used for HW/SW co-design. And for the improvement of performance the HW optimization theory such as unfolding, retiming and so forth were adapted to the cryptographic HW module conducted by FSMD. Also, the operation modes of those algorithms were implemented using C language in 8051 microprocessor, it can be compatible to various platforms. For providing reliable communication between HW/SW and preventing the time delay the improved handshake protocol was chosen for enhancing the performance of the connection between HW/SW. The improved protocol can process the communication-core and cryptography-core on the HW in parallel so that the messages can be transmitted to SW after HW operation and received from SW during encryption operation.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.