• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.510-513
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• 2007

가변길이 부호는 많은 이미지 및 영상 표준에서 폭넓게 사용되는 기법이다. 특히 국제 표준인 JVT와 중국 A/V 표준인 AVS는 엔트로피 코딩을 수행하기 위해 Exp-Golomb 코드에 기반한 UVLC(Universal Variable Length Code)를 채용하고 있다. 본 논문에서는 H.264/AVC의 엔트로피 코딩에서 사용되는 Exp-Golomb CODEC의 하드웨어 구현에 대해 연구하였다. 식의 간략화로 구현하기 어려운 log함수와 거듭제곱 연산을 하지 않으며, 첫 번째 1 검출기와 누산기 제어에 의한 배럴 쉬프터를 통하여 별도의 시간 지연 없이 부호화 및 복호화가 되도록 설계하였다. Xilinx ISE툴을 사용하여 합성하고, 보드 수준에서 PCI인터페이스를 사용하여 검증하였다. 본 논문에서 설계된 Exp-Glomb CODEC은 H.264/AVC 및 AVS와 같은 분야에서 응용이 가능할 것으로 예견된다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.280-282
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• 2005

In this paper we propose several mapping schemes for streaming video generated by state-of-the-art H.264 codec over IEEE 802.11e enabled wireless LANs. The schemes take advantage of both 802.11e's QoS mechanism and some novel features of the H.264 codec, so as to protect the most important information in terms of visual quality and reduce distortion under network congestion. The proposed methods are evaluated by means of the H.264 reference software codec, network simulation, and objective video quality measurements. Results show that the proposed methods achieve a robust and error resilient H.264 video streaming over wireless LANs than traditional best-effort streaming.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.11-17
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• 2016

In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.515-527
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• 2005

A next-generation codec should be developed to be a scalable video codec(SVC) that not only maximizes the coding efficiency but also adaptively copes with the various communication devices and the variation of network environments. To meet these requirements, Joint Video Team (JVT) of ISO/IEC and ITU-T is standardizing H.264/AVC based SVC. In this paper, we introduce research directions and status on SVC standardization and also analyze techniques and algorithms adopted in the current SVC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9A
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• pp.868-873
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• 2010

H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.110-116
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• 2009

It is very important for a DVR system to compress mass video data because they should be able to store#playback of video data. There are several high efficient DVR products using ordinary MPEG-4 compression fur data compression. But most of them support only CIF(D1/4) image, which means degraded image quality in comparison with input image source. In this paper, M-JPEG and H.264 Codec are realized using DSP. To multiple channels system M-JPEG is used for data transmission through network, and Data compression rate is improved as about 4 times as ordinary MPEG-4 compression by supporting Baseline Profile of H.264. As a result, high resolution with the width 720 pixels and the height 480 pixels can be supported.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.532-535
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• 2005

These days, many image processing techniques have been studied for effective image compression. Among those, 2D image filtering is widely used for 2D image processing. The 2D image filtering can be implemented by performing ID linear filtering separately in the direction of horizontal and vertical. Efficiency of image compression depends on what filtering method is used. Generally, circular convolution is widely used in the 2D image filtering for image processing. However it doesn't consider correlations at the region of image boundary, therefore filtering can not be performed effectively. To solve this problem. I proposed new convolution technique using Symmetric-Mirroring convolution, satisfying the 'alias-free' and 'error-free' requirement in the reconstructed image. This method could provide more effective performance than former compression methods. Because it used very high correlative data when performed at the boundary region. In this paper, pre-processing filtering in H.264 codec was adopted to analyze efficiency of proposed filtering technique, and the simulator developed by Matlab language was used to examine the performance of the proposed method.