• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.113-120
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• 2020

The multi-view video is a collection of multiple videos capturing the same scene at different viewpoints. Thus, there is an advantage of providing for user oriented view pointed video. This paper is suggested that the compression performance of layered depth image structure expression has improved by using more improved method. We confirm the data size of layer depth image by encoding H.264 technology and the each performances of reconstructed images. The H.264/AVC technology has easily extended for H.264 technology of video contents. In this paper, we suggested that layered depth structure can be applied for an efficient new image contents. We show that the huge data size of multi-view video image is decreased, and the higher performance of image is provided, and there is an advantage of for stressing error restoring.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.699-706
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• 2008

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remoye blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory sire is reduced and the throughput of the deblocking filter processing is increased. The designed deblocking filter further enhances the parallelism by simultaneously executing horizontal and vertical filtering within a macroblock in pipeline method and adopting overlap between macroblocks. The implementation result shows that the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times than that of the conventional deblocking filter. Hence the Proposed architecture of deblocking filter is able to perform real-time deblocking in high-resolution($2048{\times}1024$) video applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.790-800
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• 2009

For the improvement of coding efficiency, the H.264/AYC standard uses new coding tools such as 1/4-pel-accurate motion estimation, multiple references, intra prediction, loop filter, variable block size etc. Using these coding tools, H.264/AYC has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity was greatly increased due to these coding tools. We focus on the complexity reduction method of intra macroblock mode selection. The proposed algorithm for fast intra mode selection calculates the edge activity in transform domain, and performs fast encoding of intra frame in H.264/AYC through the fast prediction mode selection of intra4x4 and chrominance blocks. Simulation results show that the proposed method saves about 59.76% for QCIF sequences and 65.03% for CIF sequences of total encoding time, while bitrate increase and PSNR decrease are very small.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.58-66
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• 2012

Even after establishment of H.264/AVC standard, the video coding experts group (VCEG) of ITU-T has researched on development of promising coding techniques to increase coding efficiency based on the key technology area (KTA) software. Recently, the joint collaboration team video coding (JCT-VC) which was composed of the VCEG and the motion picture experts group (MPEG) of ISO/IEC is developing a next-generation video standard namely HEVC intended to gain twice efficiency than H.264/AVC. An adaptive interpolation technique, one of various next-generation techniques, reported higher coding efficiency. However, it has high computational complexity and does not deal with various error characteristics for videos. In this paper, we investigate characteristics of interpolation filters and propose an effective fixed interpolation filter bank including diverse properties of error. Experimental results is shown that the proposed method achieved bitrate reduction by 0.7% and 1.3% compared to fixed directional interpolation filter (FDIF) of the KTA and the directional interpolation filter (DIF) of the HEVC test model, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.793-797
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• 2008

To achieve flexible visual contents adaptation for multimedia communications, the ISO/IEC MPEG & ITU-T VCEG form the JVT to develop an SVC amendment for the H.264/AVC standard. JVT uses inter-layer prediction that can improve the rate-distortion efficiency of the enhancement layer. But inter-layer prediction causes computational complexity to be increased. In this paper, we propose a fast mode decision for inter frame coding. It makes use of the correlation between optimized prediction mode and its RD cost. Experimental results show that the proposed schemes save up to 38% of encoding time with a negligible coding loss and bit-rate increase.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.624-634
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• 2011

Recently, the JCT-VC is developing the next generation video coding standard that is called HEVC. HEVC has adopted many coding technologies increasing coding efficiency. For chroma interpolation, DCT-based interpolation filter showing better performance than the linear filter in H.264/AVC was adopted in HEVC. In this paper, a combined filter that utilizes the FIR filter and the linear filter in H.264/AVC is proposed to increase coding efficiency. When the proposed method is compared with DCT-based interpolation filter, the experimental results for various sequences show that the average BD-rate improvements on chroma U and V components are 0.9% and 1.1%, respectively, in the high efficiency case of random access structure, those on U and V components are 1.1% and 1.1%, respectively, in the low complexity case of random access structure, those on U and V components are 0.9% and 1.4%, respectively, in the high efficiency case of low delay structure, and those on U and V components are 1.8% and 1.8%, respectively, in the low complexity case of low delay structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1098-1107
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• 2005

The emerging H.264/AVC video coding standard improves coding performance significantly by adopting many advanced techniques. This is achieved at the expense of great increasing encoder complexity. Specifically the intra prediction using RDO examines all possible combinations of coding modes, which depend on spatial directional correlation with adjacent blocks. For 4${\times}$4 luma blocks, there are 9 modes, and for 16${\times}$16 luma and 8${\times}$8 chroma blocks, there are 4 modes, respectively. Therefore the number of mode combinations for each macroblock is 592. This paper presents a method to reduce the RDO complexity using simple directional masks and neighboring modes. According to the proposed method, we reduce the number of mode combinations to 132 at the most. Experimental results show the proposed method reduces the encoding time up to $70\%$ with negligible loss of PSNR and bitrate increase compared to the H.264/AVC exhaustive search.