• Journal of Broadcast Engineering
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• v.15 no.6
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• pp.853-867
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• 2010

Recently, thumbnail techniques are required to index a high-performance video at digital convergence-based multimedia service like IPTV and DMB. Therefore a thumbnail extraction method in H.264/AVC bitstreams has been proposed. However, thumbnail quality deterioration problem at converting the general equation of spatial domain to frequency domain which is generated by not considering about H.264/AVC transform and quantization processing and rounding-off operation in intra prediction. In this paper, we propose a new thumbnail extraction method in H.264/AVC bitstreams. The proposed scheme is based on H.264/AVC core-transform for a thumbnail extraction in frequency domain, and probability theory, intra rounding-off error compensation. Through the implementation and performance evaluation, the subjective quality difference between the output of our scheme and the output of reference decoder is negligible and better than the conventional method, and moreover PSNR gain by up to 8.66 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.119-126
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• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1182-1191
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.