• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.54-58
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• 2002

This paper describes the theoretical analysis and performance of a 2.4㎓ bulk-driven downconversion mixer, where the LO signal is input via the bulk. A mixer core designed with a 0.18$\mu\textrm{m}$ CMOS process is able to operate under 0.8V∼1V supply voltage. The RF, LO, and IF port frequencies are 2.45㎓, 2.4㎓, and 50MHz, respectively. The measurement results exhibit conversion gain of -1.8㏈, l㏈ compression point of -17㏈m and IIP3 of -4㏈m with 0㏈m LO power. The power consumption is as small as 4mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.29-34
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• 2015

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.346-349
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• 2003

A SiGe HBT MMIC double balaced up-converter has been designed and fabricated for C-band WLAN applications. The up-converter is based on the Gilbert cell mixer with an active baluns for differential inputs of LO and IF signals. The designed up-converter exhibits a conversion gain 12.5dB for a -10 dBm LO power. It also exhibits LO-RF isolation of 19.3dBc, and IF-RF isolation of 23.3 dBc at a 1-dB compression point of -14.2dBm

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1277-1281
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• 2005

FPGA has been widely used in communication system. In this paper, we made 10 layers PCB on protection of signal noise and data lose with FPGA. We analyzed about change of the data transmission speed and length according to input frequency. The length of transmission line from FPGA's output-pin to output-port on PCB board is 13cm and extended lengths for test are 30cm, 60cm and 10cm. We knew that data can be stably transmitted to 100Mbps at transmission line length of 30cm.