• Title/Summary/Keyword: Genetic Algorithm Processor

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Design of Genetic Algorithm Processor(GAP) for Evolvable Hardware (진화하드웨어를 위한 유전자 알고리즘 프로세서(GAP) 설계)

  • Sim, Kwee-Bo;Kim, Tae-Hoon
    • Journal of the Korean Institute of Intelligent Systems
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    • v.12 no.5
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    • pp.462-466
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    • 2002
  • Genetic Algorithm (GA) which imitates the process of nature evolution is applied to various fields because it is simple to theory and easy to application. Recently applying GA to hardware, it is to proceed the research of Evolvable Hardware(EHW) developing the structure of hardware and reconstructing it. And it is growing a necessity of GAP that embodies the computation of GA to the hardware. Evolving by GA don't act in the software but in the hardware(GAP) will be necessary for the design of independent EHW. This paper shows the design GAP for fast reconfiguration of EHW.

Design of state machine using Evolvable Hardware and Genetic Algorithm Processor (GAP와 진화 하드웨어를 이용한 State Machine설계)

  • 김태훈;선흥규;박창현;이동욱;심귀보
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2002.05a
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    • pp.179-182
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    • 2002
  • GA(Genetic Algorithm)는 자연계 진화를 모방한 계산 알고리즘으로서 단순하고 응용이 쉽기 때문에 여러 분야에 전역적 최적해 탐색에 많이 사용되고 있다. 최근에는 하드웨어를 구성하는 방법의 하나로서 사용되어 진화하드웨어라는 분야를 탄생시켰다. 이와 함께 GA의 연산자체를 하드웨어로 구현하는 GA processor(GAP)의 필요성도 증가하고 있다. 특히 진화하드웨어를 소프트웨어상에서 진화 시키는 것이 아닌 GAP에 의해 진화 시키는 것은 독립된 구조의 진정한 EHW 설계에 필수적이 될 것이다. 본 논문에서는 GAP 설계 방법을 제안하고 이를 이용하여 진화하드웨어로 State machine을 구현하고자 한다. State machine의 경우 구조상 피드백이 필요하기 때문에 가산기나 멀티플렉서보다는 훨씬 복잡하고 설계가 까다로운 구조이다. 제안된 방법을 통하여 명시적 설계가 어려운 하드웨어 설계에 GAP를 이용한 하드웨어의 진화에 적용함으로써 그 유용성을 보인다.

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A Linear Clustering Method for the Scheduling of the Directed Acyclic Graph Model with Multiprocessors Using Genetic Algorithm (다중프로세서를 갖는 유방향무환그래프 모델의 스케쥴링을 위한 유전알고리즘을 이용한 선형 클러스터링 해법)

  • Sung, Ki-Seok;Park, Jee-Hyuk
    • Journal of Korean Institute of Industrial Engineers
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    • v.24 no.4
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    • pp.591-600
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    • 1998
  • The scheduling of parallel computing systems consists of two procedures, the assignment of tasks to each available processor and the ordering of tasks in each processor. The assignment procedure is same with a clustering. The clustering is classified into linear or nonlinear according to the precedence relationship of the tasks in each cluster. The parallel computing system can be modeled with a Directed Acyclic Graph(DAG). By the granularity theory, DAG is categorized into Coarse Grain Type(CDAG) and Fine Grain Type(FDAG). We suggest the linear clustering method for the scheduling of CDAG using the genetic algorithm. The method utilizes a properly that the optimal schedule of a CDAG is one of linear clustering. We present the computational comparisons between the suggested method for CDAG and an existing method for the general DAG including CDAG and FDAG.

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A Study on Implementation of Evolving Cellular Automata Neural System (진화하는 셀룰라 오토마타 신경망의 하드웨어 구현에 관한 연구)

  • 반창봉;곽상영;이동욱;심귀보
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2001.12a
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    • pp.255-258
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    • 2001
  • This paper is implementation of cellular automata neural network system which is a living creatures' brain using evolving hardware concept. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogeny of natural living things. The proposed system developes each cell's state in neural network by CA. And it regards code of CA rule as individual of genetic algorithm, and evolved by genetic algorithm. In this paper we implement this system using evolving hardware concept Evolving hardware is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system is verified by applying it to time-series prediction.

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Implementation of GA Processor with Multiple Operators, Based on Subpopulation Architecture (분할구조 기반의 다기능 연산 유전자 알고리즘 프로세서의 구현)

  • Cho Min-Sok;Chung Duck-Jin
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.5
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    • pp.295-304
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    • 2003
  • In this paper, we proposed a hardware-oriented Genetic Algorithm Processor(GAP) based on subpopulation architecture for high-performance convergence and reducing computation time. The proposed architecture was applied to enhancing population diversity for correspondence to premature convergence. In addition, the crossover operator selection and linear ranking subpop selection were newly employed for efficient exploration. As stochastic search space selection through linear ranking and suitable genetic operator selection with respect to the convergence state of each subpopulation was used, the elapsed time of searching optimal solution was shortened. In the experiments, the computation speed was increased by over $10\%$ compared to survival-based GA and Modified-tournament GA. Especially, increased by over $20\%$ in the multi-modal function. The proposed Subpop GA processor was implemented on FPGA device APEX EP20K600EBC652-3 of AGENT 2000 design kit.

Enhanced Processor-Architecture for the Faster Processing of Genetic Algorithm (유전 알고리즘 처리속도 향상을 위한 강화 프로세서 구조)

  • Yoon, Han-Ul;Sim, Kwee-Bo
    • Journal of the Korean Institute of Intelligent Systems
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    • v.15 no.2
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    • pp.224-229
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    • 2005
  • Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

A GA-Based Adaptive Task Redistribution Method for Intelligent Distributed Computing (지능형 분산컴퓨팅을 위한 유전알고리즘 기반의 적응적 부하재분배 방법)

  • 이동우;이성훈;황종선
    • Journal of KIISE:Software and Applications
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    • v.31 no.10
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    • pp.1345-1355
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    • 2004
  • In a sender-initiated load redistribution algorithm, a sender(overloaded processor) continues to send unnecessary request messages for load transfer until a receiver(underloaded processor) is found while the system load is heavy. In a receiver-initiated load redistribution algorithm, a receiver continues to send unnecessary request messages for load acquisition until a sender is found while the system load is light. Therefore, it yields many problems such as low CPU utilization and system throughput because of inefficient inter-processor communications in this environment. This paper presents an approach based on genetic algorithm(GA) for adaptive load sharing in distributed systems. In this scheme, the processors to which the requests are sent off are determined by the proposed GA to decrease unnecessary request messages.

Genetic Algorithm Based Linear Region Extension for Multivariable Monopulse Tracking Systems (다변수 모노펄스 추적 시스템에서 유전 알고리즘 기반 선형구간 확장)

  • Jung, Jinwoo;Kim, Jaesin;Ryu, Young-Jae
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.2
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    • pp.272-278
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    • 2017
  • In this paper, we consider a single-channel amplitude comparison monopulse system(SCACMS). The monopulse ratio curve(MR-C) of the SCACMS can be controlled by an amplitude difference between sum and different signal, a phase difference and the coefficient of the signal processor. We first propose the SCACMS with multiple variables, and then apply a genetic algorithm to optimize the multiple variables in terms of minimizing a root mean square error. The simulation results show that when three variables of the SCACMS are jointly optimized, the linear region of the MR-C can be extended approximately 187 % compared to that of two variables.

Time-optimal Control Utilizing Beural Networks (신경회로망을 이용한 시간최적 제어)

  • Park, W.W.;J.S. Yoon
    • Journal of the Korean Society for Precision Engineering
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    • v.14 no.6
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    • pp.90-98
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    • 1997
  • A time-optimal control law for quick, strongly nonlinear systems has been developed and demonstrated. This procedure involves the utilzation of neural networks as state feedback controllers that learn the time-optimal control actions by means of an iterative minimization of both the final time and the final state error for the systems with constrained inputs and/or states. A neural identifier or a genetic algorithm identifier could be utilized for modeling the partially known systems and the unknown systems. The nature of neural networks as a parallel processor would circumvent the problem of "curwe of dimensionality". The control law has been demonstrated for both a torque input motor and a velocity input motor identified by a genetic algorithm called GENOCOPed GENOCOP.

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Realization of Digital Music Synthesizer Using a Frequency Modulation (FM 방식을 이용한 디지탈 악기음 합성기의 구현)

  • 주세철;김진범;김기두
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.7
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    • pp.1025-1035
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    • 1995
  • In this paper, we realize a real time digital FM synthesizer based on genetic algorithm using a general purpose digital signal processor. Especially, we synthesize diverse music sounds nicely using a synthesis model consisting of a single modulator and multiple carriers. Also we present genetic algorithm-based technique which determines optimal parameters for reconstruction through FM synthesis of a sound after analyzing the spectrum of PCM data as a standard music sound using FFT. Using the suggested parameter extractiuon algorithm, we extract parameters of several instruments and then synthesize digital FM sounds. To verify the validity of the parameter extraction algorithm as well as realization of a real time digital music synthesizer, the evaluation is first done by listening the sound directly as subjective test. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

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