• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• Applied Microscopy
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• v.52
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• Journal of the Korean Institute of Educational Facilities
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• v.11 no.4
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• pp.15-24
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• 2004

The purpose of this study is to suggest some alternative on site planning of elementary school through investigating the effects of geographical and urban environment on the site. For this, we selected and surveyed 35 schools in Gwangju. The results of this study are as follows. 1) We cannot find out the differences from the use of elementary schools sites on slopes of sites. However, the sunken space between H type buildings in the site slopes facing east or west and the placing the playground on the north side of the site slopes facing north have some problems 2) The number of adjacent road and surrounding environment didn't show any effect. To separate between cars and pedestrians, we need some plans to block cars on the pedestrian gateway and it is much better to intensify the parking area near the school gate that cars come in and out. 3) The degree of satisfaction on the outdoor facilities of these cases shows low level. Therefore, to use the site of schools efficiently, we should secure the spacious playground and make plans to provide some spaces around school building for the static activities of students and teachers. 4) Most of all, the site which is suitable for educational environment should be selected. and also Special Code on the urban plan should be established to develop this one.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.589-596
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• 2021

In this study, the optimum gating system was designed, and the two zinc alloy worm gears were manufactured in single process by applying a symmetrical gating system with 2 runners. The SRG ratio is set to 1 : 0.9 : 0.6, and the cross-sectional shapes such as sprue, runner and gate are designed. In order to determine whether the design of the gating system is appropriate, casting analysis was carried out. It takes 4.380 s to charge the casting 100%, 0.55 to 0.6 m/s at the gates and solidification begins after the casting is fully charged. The amount of air entrapment is 2% in the left gear and 6% in the right gear. Hot spots occurred in the center hole of the gear, and pores were found to occur around the upper part of the hole. Therefore, the design of the casting method is suitable for worm gears. CT analysis showed that all parts of worm gear were distributed with fine pores and some coarse pores were distributed around the central hole of worm gear. The yield strength and tensile strength were 220 MPa, 285 MPa, and the elongation rate was 8%. Vickers hardness is 82 HV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.29 no.4
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• pp.464-476
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• 2019

Objectives: This study aimed to assess the exposure levels of tollbooth workers to diesel particulate matter using black carbon (BC) and to find the correlations among variables associated with BC using the motor vehicle management act regulated by the Ministry of Land, Infrastructure and Transport. Methods: This study was performed over 14 days at a university in Seoul. BC levels were monitored using an aethalometer and were conducted around the breathing zones of the workers. There were three sampling locations: inside the tollbooth (front gate and rear gate) and an office as a control group. T-test, correlation, and multiple linear regression analysis were performed using SPSS. Results: The geometric mean (GM) of BC_30min concentrations in the exposure group was 2.44 ㎍/㎥, approximately 1.4 times higher than the control group (1.75 ㎍/㎥). The GM of BC_30min concentrations was 2.75 ㎍/㎥ during the heavy traffic time (9-10 am) and 2.30 ㎍/㎥ during non-heavy traffic times (p<0.001). The multiple linear regression analysis shows that the number of all types of vehicles and PM_2.5 concentrations in the atmosphere were factors increasing the GM of BC(ln(BC_30min)) concentrations (adjusted R²=0.42, p<0.001). The workers were constantly exposed to low concentrations (GM of BC_30min=2.44 ㎍/㎥), but they were exposed to peak concentrations instantly (BC_10sec=3545.04 ㎍/㎥). When the GM of BC_30min concentrations was momentarily represented as high, it was identified that a vehicle mainly using diesel fuel or an aging vehicle had passed. Conclusions: A ventilation system should be installed in the closed tollbooth or aging vehicles should be controlled so as not to pass tollbooths.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Journal of architectural history
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• v.18 no.6
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• pp.103-126
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• 2009

This study aims to discover historical trends and change of form of all stupas in India with observation of field study that is as direct as possible, by classifying, analyzing, and synthesizing the stupas. Study of Indian stupa in Korea has a number of shortcomings since only introductory partial approach has been made in order to seek the origin of Korean pagoda. This study also aims to correct errors of stupa terminology in Chinese character committed by misinterpretation of Hindi language which was established by precedent Japanese scholars several decades ago. Piled-up stupas were totally destroyed by pagans, therefore their remains tell us only of structure, material, sizeand disposition. However remains of carved stone at torana and drum give us clues as to the original form of stupa and worshipping activity, as well as change to a more luxurious form. Many rock cave stupas of India show us both simple forms matching the ascetic age of early Buddhism and luxurious changes in Mahayanan era introducing us to statues of Buddha. Indians recovered the spheric form of 'anda,' a Hindi term meaning cosmic egg, from the hemispheric form of the piled-up stupa. Therefore we might discard the erratic term of 'bokbal', which means an upset vessel. Railings and parasols became main factors of stupa design. Carved railings around stupa became a sign of divinity. Serious worshipping activity made drums long or high and created multi-embossed stripes. Bases of circular drums of some cave stupas changed their shapes to rectangular or octagonal. Single parasols became multiparasols of affluent flowerlike curved stems on carved stupa. Multistoried, elongated and high parasols of Gandhara stupas are closely related to such factors as diverse changes of form in Indian subcontinent. Four-sided torana gate and ayaka column of the circular form of original stupas suggest the rectangular form of subsequent East Asian pagoda, and higher and wider base of Indian stupas became the origin of East Asian rectangular pagoda.