• Title/Summary/Keyword: Gate oxidation anneal

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Impact of Post Gate Oxidation Anneal on Negative Bias Temperature Instability of Deep Submicron PMOSFETs (게이트 산화막 어닐링을 이용한 서브 마이크론 PMOS 트랜지스터의 NBTI 향상)

  • 김영민
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.3
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    • pp.181-185
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    • 2003
  • Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

Measurement of Interface Trapped Charge Densities $(D_{it})$ in 6H-SiC MOS Capacitors

  • Lee Jang Hee;Na Keeyeol;Kim Kwang-Ho;Lee Hyung Gyoo;Kim Yeong-Seuk
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.343-347
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    • 2004
  • High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

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Characteristics of reoxidation of nitried oxide for gate dielectric of charge trapping NVSM (전하트랩형 NVSM의 게이트 유전막을 위한 질화산화막의 재산화특성에 관한 연구)

  • 이상은;한태현;서광열
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.11 no.5
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    • pp.224-230
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    • 2001
  • The characteristics of $NO/N_2O$ annealed reoxidized nitrided oxide being studied as super thin gate oxide and gate dielectric layers of Non-Volatile Semiconductor Memory (NVSM) were investigated by Dynamic Secondary Ion Mass Spectrometry (D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS), and Auger Electron Spectroscopy (AES). The specimen was annealed by $NO/N_2O$ after initial oxide process and then rcoxidized for nitrogen redistribution in nitrided oxide. Out-diffusion of incorporated nitrogen during the wet oxidation in reoxidation process took place more strongly than that of the dry oxidation. It seems to indicate that hydrogen plays a role in breaking the Si N bonds. As reoxidation proceeds, incorporated nitrogen of $NO/N_2O$ annealed nitrided oxide is obsen-ed to diffuse toward the surface and substrate at the same time. ToF-SIMS results show that SiON species are detected at the initialoxide interface, and Si,NO species near the new $Si_2NO$ interface that formed after reoxidation. These SiON and $Si_2NO$ species most likely to relate to the origin of the state of memory charge traps in reoxidized nitrided oxide, because nitrogen dangling bonds of SiON and silicon dangling bonds of $Si_2NO$ are contained defects associated with memory effect.

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