• Design & Manufacturing
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• v.11 no.3
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• pp.13-18
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• 2017

The injection molding analysis of VCM (Voice Coil Motor) housing for smart phone cameras were performed. We conducted the analysis in terms of injection molding pressure, the formation of weld lines, flow marks, and flow patterns. The goal of the analysis was targeted for the prediction of the optimal gate locations. Because the quality of VCM housing is strongly dependent on the precise control of the camera lens by its nature, we focused on the lens guiding lanes in the VCM housing. We first calculated the maximum injection molding pressure in terms of the filled volumes. The injection molding pressure were calculated within 146MPa at about 90% volume filled. We also investigated the possibility of the occurrence of design-related defects such flow marks, weld lines. Filling patterns regarding the design of the gate locations were delineated to find the weld lines. Throughout the simulations, the final deformations of the lens guiding lanes for the VCM housing were calculated. The deformations distribute ranging from $0.5{\mu}m$ to $2.50{\mu}m$, which were used to find the optimal design of the gates.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.2
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• pp.86-92
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• 2021

Usually, the die-cast components used in small mobile devices require finishing processes, such as computer numerically controlled coating. In such cases, porosity is the most important defect. The shape of the molten aluminum that passes through the runner and gate in a mold is the one of the factors that influences gas porosity. To define the spurt index, which numerically indicates the shape of molten aluminum after the gate, Reynolds number and Ohnesorge number are used. Before die fabrication, computer-aided engineering analysis is performed to optimize the filling pattern. Finally, X-ray and surface inspection are performed after casting and machining to evaluate how the spurt index affects porosity and other product parameters. Based on the results obtained herein, a new gating system design process is suggested.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.570-574
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• 2008

The 'gate non-stop system utilizing RFID (900MHz)', which is the core of this research, is the system which connects RFID to recognize the vehicle information without stopping when a vehicle (trailer) passes a gate to carry in or out containers in a terminal and automatically provides the container information provided by the terminal for the RFLDU device installed in the vehicle.In order to design and implement this, the RFID technical section uses a UHF band (900MHz) RFID tag and a reader and implements a RFID middleware and an application program for smooth data collection and execution (operation). In addition, the system stability was verified through experiments and operations of the system implemented in this research at real harbors/quays, and based on the verified result, the maximization of vehicle (trailer) and terminal productivity and the reduction of distribution cost are expected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.339-348
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• 2017

Power supply for railway cars can be divided into propulsion system power supply and auxiliary power units (APU). The propulsion system power supply is for propulsion of railway cars, and regenerative braking; the APU provides power for the air compressor, lighting, car control and other auxiliary parts. According to high voltage and high current specifications, generally, an insulated-gate bipolar transistor (IGBT) is adopted for the switching component. For appropriate switching operation, a gate driver unit (GDU) is essentially required. In this paper, the technical trends of GDU for railway cars are analyzed and a design consideration for IGBT GDU is described.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.291-300
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• 2017

Quantum-dot cellular automata(QCA) is a computing model designed to be similar to cellular automata, and an alternative technology for next generation using high performance and low power consumption. QCA is undergoing various studies with recent experimental results, and it is one of the paradigms of transistors that can solve device density and interconnection problems as nano-unit materials. An XOR gate is a gate that operates so that the result is true when either one of the logic is true. The proposed XOR gate consists of five layers. The first layer consists of OR gates, the third and fifth layers consist of AND gates, and the second and fourth layers are designed as passages in the middle. The half adder consists of an XOR gate and an AND gate. The proposed half adder is designed by adding two cells to the proposed XOR gate. The proposed half adder consists of fewer cells, total area, and clock than the conventional half adder.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.