• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.3
• /
• pp.387-393
• /
• 1987

The introduction of a digiral subscriber loop transmission system necessitates an optimized line interface solution. To meet this objective an adaptive line equalizer has been developed. The equalizer can be compensated up to 42 dB line loss at 200KHz, and operated up to 3.2 Km transmission length (0.4 mm\ulcornercable)at a rate of 400Kb/s. This has been builted using a variable \ulcorner equalizer to compensate a frequency-attenuation characteristics of metallic cable, an AGC (automatic gain control) circuits with simple control algorithm, and various filters to minimize a transmission constraints over subscriber loop. The purpose of this paper is to present a short description of a design of the adaptive line equalizer with a summary of implementation results. Some design concepts and considerations which results in an implementation of the equalizer are also given.

• Journal of Broadcast Engineering
• /
• v.8 no.1
• /
• pp.3-10
• /
• 2003

This paper proposes a variable-Q digital graphic equalizer in which each equalizer filter has different Q-factor depending on the band as well as the gain. The proposed equalizer demonstrates the symmetric frequency response over the audible frequency range. While maintaining the similar level of hardware complexity, the proposed equalizer yields an actual response that is quite close to the desired one, as compared with the conventional equalizers. Also, we investigate how the performance is affected by the center frequencies of the filters.

• Journal of Korea Society of Industrial Information Systems
• /
• v.16 no.4
• /
• pp.19-26
• /
• 2011

Relay-assisted multiple input multiple output (MIMO) technique has become a promising candidate for next generation broadband wireless communications. In this paper, we propose maximum ratio combining (MRC) minimum mean-square-error (MMSE) equalization for single carrier-frequency domain equalizer (SC-FDE) in amplify-and-forward (AF) relaying networks. The performance of SC-FDE system can be improved considerably by achieving both the diversity gain and the MMSE equalization gain when the signals from source-destination (S->D) and source-relay-destination (S->R->D) are combined and equalized by means of the MMSE criteria. We find the weighting coefficients of MRC combining and the tap coefficients of MMSE equalizer for SC-FDE in AF relaying networks. Simulation results show that the proposed relay-based system considerably outperforms the conventional SC-FDE system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.5
• /
• pp.50-57
• /
• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• Journal of information and communication convergence engineering
• /
• v.7 no.2
• /
• pp.113-118
• /
• 2009

This paper is about design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the power line communication (PLC) system. The Tchebycheff gain function algorithm is represented to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.119-124
• /
• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.3
• /
• pp.1280-1285
• /
• 2017

In this paper, we consider iterative soft-decision feedback equalizers (sDFE), a.k.a. turbo equalizers for single-carrier transmission. Turbo equalizer takes log-likelihood ratio (LLR) feedback from channel decoder and convert the LLR into symbol estimates and variances to be used for the LLR update at the sDFE. Specifically, we consider both time domain and frequency-domain sDFE and compare their performances. The results shows that frequency-domain sDFE performs better than time-domain one and also that considerable gain can be obtained especially when the channel has deep nulls.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.2 s.105
• /
• pp.95-100
• /
• 2006

In this paper, we designed amplitude equalizer which is composed of amplifier, complementary shaping filter and attenuator in order to improve flatness of high order bandpass filter. We modified Chebyshev polynomial and calculated the prototype elements for complementary shaping filters by network synthesis. The amplitude equalizer is realized that it connects the 4th order complementary shaping filter designed by using calculated the prototype elements to the amplifier compensating for insertion loss and improving return loss, and with the attenuator for gain control. Using proposed amplitude equalizer, We certificated improvement in flatness of 13th order bandpass filter at WiBro band.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.11 no.11
• /
• pp.1053-1060
• /
• 2016

This paper proposes an adaptive equalizer with the digitally controlled active variable capacitor. An equalizing amplifier consists of a main amplifier and a source degeneration RC filter which is implemented using the digitally controlled active variable capacitor for area efficiency and linear loss compensation. The active capacitor changes its capacitance by the amplifier gain control, which is based on miller effect. In the simulated results, the proposed equalizer compensates the high frequency loss and extends the data eye width from 0.31 UI to 0.64 UI.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.33-39
• /
• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.