• 전기학회논문지P
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• 제64권3호
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• pp.111-115
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• 2015

Recently, protection coordination issues can occur due to increased fault current in power system when power system being changed radial power system to grid system such as loop power system, micro grid and smart grid. This paper analyzed Recloser-Fuse coordination in loop power distribution system with Superconducting Fault Current Limiters(SFCLs) when single line ground fault occur in loop power distribution system with SFCLs. We analyzed Recloser-Fuse Coordination in radial power distribution system and changed coordination caused by increased Fault current because of loop system when single line ground fault occur in power distribution system. This paper simulated to improve changed coordination using SFCLs in loop power distribution system. Power distribution system, SFCLs and protective devices are modeled using PSCAD/EMTDC.

• 한국전기전자재료학회논문지
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• 제33권3호
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• pp.201-207
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• 2020

With the expansion in the use of DC power systems and increased need for system maintenance, the development of measurement devices for maintenance requires high stability. Of the different kinds of DC current measurement devices, the single-shot measurement device causes the input signal of the current measuring unit to initially generate a high inrush current. The high inrush current flows into the signal processor of the meter, shortening the life of the internal fuses and causing failure. Therefore, in this study, the I²t value for increasing the durability of the fuse is designed using the available wire diameter. Operating characteristics for 210~400% over-current of the rated current, which is relatively low over-current, are realized by the plating of low melting tin metal. As a result, a method of designing a fuse element for a DC power supply, which improves the safety of the DC current measurement device by blocking the failure caused by the inrush current, is presented.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권3호
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• pp.185-191
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• 1999

The fuse used in the high voltage distribution line often fails due to the active ionization caused by the strong electric field at fuse terminal. To suppress the ionization at the high voltage and high capacity current limiting fuse, the particle size and compactness of silica sand, the design, length, notch number and material of element, the diameter and length of fuse body must be considered carefully. However, these are not many proper which is treated with the inherent interrupting characteristics from many parameters at present. Because of these reasons, time and effort are needed to develop the new type fuse by the fuse designers in relation with the inherent characteristics from each of parameters. In this paper we choose 7 parameters with weight value based on study and experimentation and analyzed the characteristics of arcing period. In addition, we proposed the experimental method to experimentation and analyzed the characteristics of arcing period. In addition, we proposed the experimental method to extract the optimal design parameters with minimal effort as related the mutual effect from each of the parameters.

• 한국정보통신학회논문지
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• 제14권11호
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• pp.2541-2547
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• 2010

본 논문에서는 대기 상태에서 저전력 eFuse OTP 메모리 IP틀 구현하기 위해 속도가 문제가 되지 않는 반복되는 블록 회로에서 1.2V 로직 트랜지스터 대신 누설 (off-leakage) 전류가작은 3.3V의 MV (Medium Voltage) 트랜지스터로 대체하는 설계기술을 제안하였다. 그리고 읽기 모드에서 RWL (Read Word-Line)과 BL의 기생하는 커패시턴스를 줄여 동작전류 소모를 줄이는 듀얼 포트 (Dual-Port) eFuse 셀을 사용하였다. 프로그램 전압에 대한 eFuse에 인가되는 프로그램 파워를 모의실험하기 위한 등가회로를 제안하였다. 하이닉스 90나노 CMOS 이미지 센서 공정을 이용하여 설계된 512비트 eFuse OTP 메모리 IP의 레이아웃 크기는 $342{\mu}m{\times}236{\mu}m$이며, 5V의 프로그램 전압에서 42개의 샘플을 측정한 결과 프로그램 수율은 97.6%로 양호한 특성을 얻었다. 그리고 최소 동작 전원 전압은 0.9V로 양호하게 측정되었다.

• 전자공학회논문지 IE
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• 제47권4호
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• pp.28-33
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• 2010

본 연구에서는 Fuse의 캡 tinning 후 불량선별 공정을 자동화하기 위한 알고리즘을 설계하였다. 퓨즈 제조공정에서 퓨즈의 캡에 납을 삽입하는 것을 tinning 공정이라 한다. Tinning 후 불량선별을 하는 공정에서 기존에는 사랑의 육안에 의해 검사 하였으나, 본 연구에서는 CCD 카메라를 이용하여 불량을 검사 하는 알고리즘을 설계 하였다. 검사 알고리즘은 캡의 내부를 촬영한 후 촬영된 이미지를 영상처리 과정을 거쳐서, 캡 내부의 납의 분포도를 검사하고 기준값과 비교하여 불량을 선별하도록 하였다.

• 한국정보전자통신기술학회논문지
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• 제8권4호
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• pp.310-318
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• 2015

본 논문에서는 cell 사이즈가 작은 dual port eFuse OTP(One-Time Programmable)를 사용하면서 VREF(Reference Voltage) 회로를 eFuse OTP IP(Intellectual Property)에 하나만 사용하고 S/A(Sense Amplifier) 기반의 D F/F을 사용하는 BL(Bit-Line) 센싱 회로를 제안하였다. 제안된 센싱 기술은 read current를 6.399mA에서 3.887mA로 줄일 수 있다. 그리고 아날로그 센싱을 하므로 program-verify-read 모드와 read 모드에서 프로그램된 eFuse의 센싱 저항은 각각 $9k{\Omega}$, $5k{\Omega}$으로 낮출 수 있다. 그리고 설계된 32비트 eFuse OTP 메모리의 레이아웃 면적은 $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213mm^2$)으로 저면적 구현이 가능한 것을 확인하였다.

• 한국조명전기설비학회지:조명전기설비
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• 제11권6호
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• pp.74-80
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• 1997

본 논문에서는 저압 배전용 전선퓨즈의 I-t 특성을 다루었다. 전선퓨즈 엘리먼트는 과전류 영역을 담당하는 낮은 온도 용융영역(LTME)과, 대전류 영역을 담당하는 높은 온도 용융영역(HTME)으로 나누어 진다. 이들부분에 의하여 퓨즈의 용단특성이 결정되는 것이다. 따라서 이들 부분에 대한 열적, 전기적인 특성을 시뮬레이션하므로서, 퓨즈 엘리먼트 설계의 타당성을 이론적으로 검증하였다. 유한요소법(Finite Element Method)을 이용하여 전선퓨즈의 I-t특성을 시뮬레이션 하였다. 그리고 시뮬레이션 결과와 실혐결과를 비교해 보았을 때 대전류영역과 소전류영역에서의 상당히 유사한 결과를 얻을 수 있었다.

• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.673-677
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• 2004

We present the basic properties of a superconductive fuse (SF) based on YBCO/Au films. The SF consists of YBCO stripes covered with Au layers for current shunt. The fault current was limited to a designed value in less than 0.4 msec by resistance development in YBCO/Au upon quenching. This enabled the SF to transfer small fault power and the suppressed current was sustained for more than 0.5 msec while Au layer melting and arcing. The arcing time was less than 2.5 msec, that is short enough to do self-interruption. Under the source voltage of 100 $V_{rms}$, the longer the duration time of fault current was, the shorter its discharge time was. The duration time of fault current and its discharge time were reduced by increased voltages in the range of 200 - 300 $V_{rms}$. We thought that this was because the quench propagation was limited by local melting generated with higher voltage.age.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 연구회
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• pp.161-163
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• 2001

We present the basic properties of a superconducting current limiting fuse (SCLF) based on YBCO/Au films. The SCLFs consists of YBCO stripes covered with Au layers for current shunt. Under the source voltage of 100 $V_{rms}$, the longer the duration time of fault current was, the shorter its discharge time was. The duration time of fault current and its discharge time were reduced by increased voltages in the range of 200 - 300 $V_{rms}$. We thought that this was because the quench propagation was limited by local melting generated with higher voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).