• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.59-64
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• 2013

In this paper, a capacitor multiplier with good frequency characteristics has been proposed. Effective capacitance of conventional capacitor multiplier decreases as frequency increases due to internal series resistance. On the other hand, the proposed capacitor multiplier using cascode structure has smaller internal resistance, thus shows good frequency characteristics. Conventional and proposed capacitor multiplier were fabricated using Samsung $0.13{\mu}m$ CMOS process and frequency characteristics of capacitor multipliers were measured using LPF. Measurement results show that the conventional capacitor multiplier has maximum 53% of capacitance error, however the proposed multiplier has less than 10% of capacitance error for the frequency change from 100kHz to 1MHz.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.49-55
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• 2015

This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.5
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• pp.188-192
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• 1984

A method of frequency multipling of square waveforms is described and an integrable frequency multiplier which is fully compatible with IC technology, and made use of only bipolar transistors and resistors is proposed. The circuit is composed of only integrable time delay circuits and exclusive OR gates. Hence the circuit shows some useful characteristics.

• Journal of IKEEE
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• v.22 no.4
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• pp.1088-1092
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• 2018

In this paper, we propose a dual-mode frequency tripler using push-push and stacked FET structures. The proposed circuit can operate either in frequency multiplier mode or in amplifier mode. In the frequency multiplier mode, push-push frequency multiplication is achieved by allowing input signals with particular phase shifts. In the amplifier mode, the device operates as a distributed amplifier to obtain high gain. Also both modes were designed using stacked FET structure. The designed circuit showed frequency tripled output power of 9.7 dBm at 2.4 GHz with the input at 800 MHz. On the other hand, in the amplifier mode, the device showed 8.9 dB of gain to generate 19.5 dBm at 800 MHz.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.294-297
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• 2003

This paper describes the design and the simulation of a frequency doubler for millimeter-wave applications using distributed amplifier technology. The designed frequency multiplier has 10% bandwidth at 58GHz output. This paper investigates nonlinear analysis of pHEMT frequency multipliers utilizing AM-AM and AM-PM distortion characteristics of frequency doubler. The conversion loss is 2.1dB and harmonic suppression is larger than 18.6dBc with 5dBm input power

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.725-731
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• 2006

A novel design of frequency multiplier using a feedforward technique and a defected ground structure(DGS) is proposed. The feedforward loop in the proposed frequency multiplier suppresses the fundamental component $(f_0)$, the dumb-bell or spiral shaped DGS diminish unwanted harmonics such as second, third and fourth. Due to the combination of the feedforward structure and the DGS, only the multiplied frequency component$(2f_0,\;3f_0,\;4f_0)$ appears at the output port and the other unwanted components are suppressed excellently. The frequency multiplier is designed at 1 GHz $(f_0)$, by the proposed technique and measured. The measured output power of $2f_0,\;3f_0$ and $4f_0$ is -2.59 dBm, -5.36dBm and -4.57dBm, respectively, when the input power is 0dBm.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.66-73
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• 2010

This paper proposes the frequency multiplier using diplexer based on CRLH transmission line with dualband characteristic. The diplexer is separated the output signals of harmonic generator, which is generated the harmonic signals using nonlinear device. The diplexer consists of the inphase power divider, 0o/90o phase controller and dual-band quadrature hybrid coupler. This send out the selecting output signals of the harmonic signals and suppresses out of signals. To validate a function of multiplier, the harmonic generator and diplexer with 2 GHz and 3 GHz operating frequency range is implemented. As a result, the proposed frequency multiplier is operated normally.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1153-1157
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• 2004

This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.