• Journal of electromagnetic engineering and science
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• 제7권4호
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• pp.175-182
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• 2007

In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.

• 산업기술연구
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• 제28권A호
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• pp.177-184
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• 2008

A low loss frequency doubler operated on low power for the RFID harmonic tags is presented. Using the excellent nonlinear characteristics of the Schottky barrier diode and proper matching networks between the diode and ports, the low conversion loss of the harmonic tag is accomplished. This doubler could be used to increase the detectable distance of the conventional RFID system adopted harmonic tags.

• Journal of electromagnetic engineering and science
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• 제4권2호
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• pp.87-92
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• 2004

A millimeter-wave distributed frequency doubler has been designed with distributed block and frequency tunable output reflectors. The simulated conversion loss of 9.5 ㏈ to 7.7 ㏈ from 54.6 ㎓ to 62.4 ㎓ output frequencies is achieved with fundamental and third harmonic signal rejections of more than 10 ㏈c. The fabricated chip has the size of 1.2 mm${\times}$1.0 mm. Some measured results of frequency and bias dependent characteristics are presented for the fabricated PHEMT MMIC frequency doubler. The designed doubler has two transistors, and if one of the transistors fails the doubler unit still operates with reduced gain. The failure effect of the PHEMT has been simulated, and compared to the measured data of which one PHEMT is not operating properly.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.147-152
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• 2017

This paper presents a frequency doubler operating at G-band that exceeds the maximum oscillation frequency ($f_{max}$) of the given transistor technology. A common-source transistor is biased on class-B to obtain sufficient output power at the second harmonic frequency. The input and output impedances are matched to achieve high output power and high return loss. The frequency doubler is fabricated in a commercial 150-nm GaAs pHEMT process and obtains a measured conversion gain of -5.5 dB and a saturated output power of -7.5 dBm at 184 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• 한국통신학회논문지
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• 제30권2A호
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• pp.122-128
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• 2005

본 논문에서는 고조파 억압 특성 개선을 위한 저잡음 병렬 궤환형 발진기 (Parallel feedback oscillator)와 주파수 체배기 (frequency doubler)를 설계 및 제작하였다. 주파수 체배를 위한 발진기의 기본 주파수를 유전체 공진기 (DR: Dielectric Resonator) 여파기와 능동소자 사이에서 얻음으로써 불요 고조파를 현저히 억압하였다. 발진기의 기본 주파수 신호는 고조파 신호를 억압하기 위한 부가적인 대역 통과 여파기가 필요치 않으며 곧바로 주파수 체배기의 입력단으로 인가되어 주파수 체배기의 입력 정합 회로가 간단하다. 측정된 발진기의 고조파 억압 특성은 -47.7 dBc이고 주파수 체배기를 이용하였을 때 24.0 GHz 에서의 기본 주파수 억압 특성은 -37.5 dBc이다. 위상 잡음 특성은 중심 주파수에서 10 KHz와 100 KHz 떨어진 곳에서 각각 -80.3 dBc/Hz와 -93.5 dBc/Hz이다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.7-10
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• 2002

This paper presents a design of 24㎓ GaAs MESFET voltage controlled oscillator using a dielectric resonator(DR) and a frequency doubler. DR modeling has been done to get the effects of resonator size and the gap from transmission line by HFSS at 12㎓, and frequency doubler is used to get 24㎓ Output.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.342-345
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• 2014

An active frequency doubler monolithic microwave integrated circuit (MMIC) for E-band transceiver applications is presented in this letter. This MMIC has been fabricated in a commercial $0.1-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (pHEMT) process on a 2-mil thick substrate wafer. The fabricated MMIC chip has been measured to have a high output power performance of over 13 dBm with a high fundamental leakage suppression of more than 38 dBc in the frequency range of 71 to 86 GHz under an input signal condition of 10 dBm. A microstrip coupled line is used at the output circuit of the doubler section to implement impedance matching and simultaneously enhance the fundamental leakage suppression. The fabricated chip is has a size of $2.5mm{\times}1.2mm$.

• Journal of electromagnetic engineering and science
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• 제16권4호
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• pp.229-231
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• 2016

A 180-GHz signal source based on a 65-nm CMOS technology has been developed in this study. The 180-GHz signal source consists of a 90-GHz fundamental-mode Colpitts oscillator and a 180-GHz frequency doubler. A coupled-line is employed to couple two oscillator cores for generating a differential signal, which is delivered to the input of the differential-mode doubler. The fabricated signal source operates from 181.2 to 182.4 GHz with output power varying from -15.3 to -10.8 dBm. The peak output power was -10.53 dBm at 181.3 GHz with a DC power consumption of 42 mW, and the associated phase noise was -71 dBc/Hz at 1 MHz offset.

• 한국통신학회논문지
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• 제32권2A호
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• pp.213-219
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• 2007

본 논문에서는 입력단에 위상 지연 선로와 하모닉 출력단에 $90^{\circ}$ 하이브리드 결합기를 사용하여 억압특성을 개선한 새로운 구조의 주파수 체배기를 설계 및 제작하였다. 제안된 구조의 주파수 체배기는 출력전력 결합특성과 기본주파수의 억압특성을 개선하였다. $2.13{\sim}2.15GHz$의 주파수를 2체배 하여 $4.26{\sim}4.30GHz$의 신호원을 얻는 능동주파수 2체배기이며, 입력전력이 10dBm일 때 0.79dB 변환이득과 기본주파수에서 -55.54dBc, 3체배 주파수 6.42GHz에서 -44.76dBc, 4체배 주파수 8.56GHz에서 -39.19dBc의 개선된 억압특성값 얻을 수 있었다.