• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.175-182
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• 2007

In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.

• Journal of Industrial Technology
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• v.28 no.A
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• pp.177-184
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• 2008

A low loss frequency doubler operated on low power for the RFID harmonic tags is presented. Using the excellent nonlinear characteristics of the Schottky barrier diode and proper matching networks between the diode and ports, the low conversion loss of the harmonic tag is accomplished. This doubler could be used to increase the detectable distance of the conventional RFID system adopted harmonic tags.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.87-92
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• 2004

A millimeter-wave distributed frequency doubler has been designed with distributed block and frequency tunable output reflectors. The simulated conversion loss of 9.5 ㏈ to 7.7 ㏈ from 54.6 ㎓ to 62.4 ㎓ output frequencies is achieved with fundamental and third harmonic signal rejections of more than 10 ㏈c. The fabricated chip has the size of 1.2 mm${\times}$1.0 mm. Some measured results of frequency and bias dependent characteristics are presented for the fabricated PHEMT MMIC frequency doubler. The designed doubler has two transistors, and if one of the transistors fails the doubler unit still operates with reduced gain. The failure effect of the PHEMT has been simulated, and compared to the measured data of which one PHEMT is not operating properly.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.147-152
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• 2017

This paper presents a frequency doubler operating at G-band that exceeds the maximum oscillation frequency ($f_{max}$) of the given transistor technology. A common-source transistor is biased on class-B to obtain sufficient output power at the second harmonic frequency. The input and output impedances are matched to achieve high output power and high return loss. The frequency doubler is fabricated in a commercial 150-nm GaAs pHEMT process and obtains a measured conversion gain of -5.5 dB and a saturated output power of -7.5 dBm at 184 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.122-128
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• 2005

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.7-10
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• 2002

This paper presents a design of 24㎓ GaAs MESFET voltage controlled oscillator using a dielectric resonator(DR) and a frequency doubler. DR modeling has been done to get the effects of resonator size and the gap from transmission line by HFSS at 12㎓, and frequency doubler is used to get 24㎓ Output.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.342-345
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• 2014

An active frequency doubler monolithic microwave integrated circuit (MMIC) for E-band transceiver applications is presented in this letter. This MMIC has been fabricated in a commercial $0.1-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (pHEMT) process on a 2-mil thick substrate wafer. The fabricated MMIC chip has been measured to have a high output power performance of over 13 dBm with a high fundamental leakage suppression of more than 38 dBc in the frequency range of 71 to 86 GHz under an input signal condition of 10 dBm. A microstrip coupled line is used at the output circuit of the doubler section to implement impedance matching and simultaneously enhance the fundamental leakage suppression. The fabricated chip is has a size of $2.5mm{\times}1.2mm$.

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.229-231
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• 2016

A 180-GHz signal source based on a 65-nm CMOS technology has been developed in this study. The 180-GHz signal source consists of a 90-GHz fundamental-mode Colpitts oscillator and a 180-GHz frequency doubler. A coupled-line is employed to couple two oscillator cores for generating a differential signal, which is delivered to the input of the differential-mode doubler. The fabricated signal source operates from 181.2 to 182.4 GHz with output power varying from -15.3 to -10.8 dBm. The peak output power was -10.53 dBm at 181.3 GHz with a DC power consumption of 42 mW, and the associated phase noise was -71 dBc/Hz at 1 MHz offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.213-219
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• 2007

In this paper, A novel structure of frequency doubler using Phase Delay line and $90^{\circ}$ Hybrid coupler at harmonic output have been designed and implemented to improve suppression. Proposed structure of frequency doubler improve output. coupling and fundamental suppression. Active frequency doubler with band from $2.13{\sim}2.15GHz\;to\;4.26{\sim}4.3GHz$ was designed and fabricated with 10dBm input power, 0.79dB conversion gain and -55.54dBc suppression at fundamental frequency, -44.76dBc suppression at third harmonic frequency 6.42GHz and -39.18dBc suppression at fourth harmonic frequency 8.56GHz.